Hi Simon, WE have investigated this issue (I work for INSBU Engineering that designed these ASICs), and the issue is not an ASIC bug, but a wrong flag set by SW, which will be fixed. I will re-open the bug and we will get it resolved. We will reach out to you through the TAC and account team offline to resolve this ASAP using workaround , until the fixed SW is available. If needed, we can make an RPM patch available for you.
Should you have any questions, please feel free to unicast me. thanks sukumar On 12/2/16, 5:42 AM, "cisco-nsp on behalf of Simon Lockhart" <[email protected] on behalf of [email protected]> wrote: On Fri Dec 02, 2016 at 03:40:03PM +0200, Mark Tinka wrote: > Good to know. > > We are currently considering the 9508 for a particular role (Layer 2 > only), and I know they are based on the Broadcom chip. I'm guessing this > is where the limitation is coming from, yes? The 92160 is based on Cisco silicon (ASE3, I think). So they can't even blame Broadcom :) Simon _______________________________________________ cisco-nsp mailing list [email protected] https://puck.nether.net/mailman/listinfo/cisco-nsp archive at http://puck.nether.net/pipermail/cisco-nsp/ _______________________________________________ cisco-nsp mailing list [email protected] https://puck.nether.net/mailman/listinfo/cisco-nsp archive at http://puck.nether.net/pipermail/cisco-nsp/
