This is an automated email from the ASF dual-hosted git repository. xiaoxiang781216 pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 9ae402476982404aeab43cfdbb2a8c3504a40df2 Author: raiden00pl <[email protected]> AuthorDate: Fri Oct 30 13:18:49 2026 +0100 boards/nucleo-n657x0-q: Define the LPTIM kernel clocks. LPTIM1 runs on PCLK1 and LPTIM2-5 on PCLK4, the reset values of the RCC_CCIPR12 LPTIM source selections; PCLK4 equals HCLK (PPRE4 /1). Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- boards/arm/stm32n6/nucleo-n657x0-q/include/board.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h b/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h index 82062563dd1..fb0edb067db 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h +++ b/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h @@ -89,6 +89,16 @@ #define STM32_TIM13_CLKIN STM32_APB1_TIM_FREQUENCY #define STM32_TIM14_CLKIN STM32_APB1_TIM_FREQUENCY +/* LPTIM kernel clocks (RCC_CCIPR12 LPTIMxSEL reset values): LPTIM1 on + * PCLK1, LPTIM2-5 on PCLK4 (= HCLK, PPRE4 /1) + */ + +#define STM32_LPTIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_LPTIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_LPTIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_LPTIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_LPTIM5_CLKIN STM32_HCLK_FREQUENCY + /* I/O voltage domains ******************************************************/ /* GPIO port E (USART1 TX/RX on PE5/PE6) is on the VddIO2 and VddIO3
