zyfeier commented on code in PR #21504: URL: https://github.com/apache/nuttx/pull/21504#discussion_r4491180182
########## arch/tricore/src/common/tasking/tricore_vectors.asm: ########## @@ -0,0 +1,137 @@ +;**************************************************************************** +; arch/tricore/src/common/tasking/tricore_vectors.asm +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed to the Apache Software Foundation (ASF) under one or more +; contributor license agreements. See the NOTICE file distributed with +; this work for additional information regarding copyright ownership. The +; ASF licenses this file to you under the Apache License, Version 2.0 (the +; "License"); you may not use this file except in compliance with the +; License. You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +; License for the specific language governing permissions and limitations +; under the License. +; +;**************************************************************************** +; +; TASKING (astc) version of gnu/tricore_vectors.S, same code and layout; see +; there for the description. astc does not run the C preprocessor, so the +; CORE_ID offset (TRICORE_CPU_CORE_ID in arch/csfr.h) is written out. The +; tables are protected, as nothing references them by symbol. +; +;**************************************************************************** + + .extern tricore_trapcall + .extern tricore_svcall + .extern tricore_doirq + .extern tricore_fcu_recover + .extern g_tricore_fcu_pool + +TRAPSLOT .macro cls, entry + svlcx + mov d5, #cls + j entry + .align 32 + .endm + +TRAPJUMP .macro entry + j entry + .align 32 + .endm + +TRAPTAB .macro cpu, label + .sdecl ".text.traptab_cpu\cpu",code,protect + .sect ".text.traptab_cpu\cpu" + .align 256 + .global label +label: + TRAPSLOT 0, tricore_trap_entry + TRAPSLOT 1, tricore_trap_entry + TRAPSLOT 2, tricore_trap_entry + TRAPJUMP tricore_ctx_entry + TRAPSLOT 4, tricore_trap_entry + TRAPSLOT 5, tricore_trap_entry + TRAPSLOT 6, tricore_syscall_entry + TRAPSLOT 7, tricore_trap_entry + .endm + + TRAPTAB 0, tricore_trap_vectors_cpu0 + TRAPTAB 1, tricore_trap_vectors_cpu1 + TRAPTAB 2, tricore_trap_vectors_cpu2 + TRAPTAB 3, tricore_trap_vectors_cpu3 + TRAPTAB 4, tricore_trap_vectors_cpu4 + TRAPTAB 5, tricore_trap_vectors_cpu5 + +INTVEC .macro cpu, label + .sdecl ".text.intvec_cpu\cpu",code,protect + .sect ".text.intvec_cpu\cpu" + .align 32 + .global label Review Comment: ditto -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
