zhangyu-duck commented on code in PR #21504: URL: https://github.com/apache/nuttx/pull/21504#discussion_r4491189050
########## arch/tricore/src/common/gnu/tricore_vectors.S: ########## @@ -0,0 +1,153 @@ +/**************************************************************************** + * arch/tricore/src/common/gnu/tricore_vectors.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Trap vector table, one per core. BTV points at the table of the core in + * use; the linker script keeps the .traptab_cpuN section of that core. + * + * Each 32-byte slot saves the lower context and enters the common trap + * entry with the trap class in %d5; the hardware has put the TIN in %d15 + * and the trap return address in %a11. The entry builds a struct + * tricore_trap_s on the stack and enters the handler with jli, so the + * handler sees PCXI pointing at the lower context of the trapped code. + * The handler returns with ji %a11, then the entry restores the lower + * context and returns from the trap. + * + * Context management traps go through tricore_ctx_entry first: on a free + * context list underflow (FCU, TIN 4) there is no free CSA, so svlcx + * cannot run. tricore_fcu_entry then saves the trapped context into the + * pool registered with tricore_fcu_register_pool() and continues in + * tricore_fcu_recover(). The saved %a4 is lost, as the entry uses it, and + * so is %sp when the trap switched to the interrupt stack. Without a pool + * the core stops in tricore_fcu_entry. + * + * The interrupt vector, one per core, saves the lower context and enters + * tricore_doirq the same way. The startup code sets the priority bits + * of BIV, so every interrupt priority enters this one vector. + * + * tasking/tricore_vectors.asm is the same code in the TASKING syntax. + ****************************************************************************/ + +#include <arch/csfr.h> + + .macro TRAPSLOT cls, entry + svlcx + mov %d5, \cls + j \entry + .p2align 5 + .endm + + .macro TRAPJUMP entry + j \entry + .p2align 5 + .endm + + .macro TRAPTAB cpu + .section .traptab_cpu\cpu, "ax", %progbits + .p2align 8 + .global tricore_trap_vectors_cpu\cpu +tricore_trap_vectors_cpu\cpu: Review Comment: what about remove cpu flag, during bmp mode, all core share one inttable/traptable, all core share one name ########## arch/tricore/src/common/tricore_trapcall.c: ########## @@ -39,328 +40,276 @@ #include "tricore_internal.h" -#include "IfxCpu_Trap.h" - /**************************************************************************** - * Private Data + * Pre-processor Definitions ****************************************************************************/ -static IfxCpu_Trap g_trapinfo; +/* Trap classes and trap identification numbers (TIN), as named in the + * TriCore architecture manual. + */ + +#define TRICORE_TRAP_CLASS_MMU 0 /* Memory management */ +#define TRICORE_TRAP_CLASS_PROT 1 /* Internal protection */ +#define TRICORE_TRAP_CLASS_INSN 2 /* Instruction errors */ +#define TRICORE_TRAP_CLASS_CTX 3 /* Context management */ +#define TRICORE_TRAP_CLASS_BUS 4 /* System bus and peripheral errors */ +#define TRICORE_TRAP_CLASS_ASSERT 5 /* Assertion */ +#define TRICORE_TRAP_CLASS_NMI 7 /* Non-maskable interrupt */ + +#define TRICORE_TIN_VAF 0 /* Class 0: virtual address fill */ +#define TRICORE_TIN_VAP 1 /* Class 0: virtual addr protection */ + +#define TRICORE_TIN_PRIV 1 /* Class 1: privilege violation */ +#define TRICORE_TIN_MPR 2 /* Class 1: protection read */ +#define TRICORE_TIN_MPW 3 /* Class 1: protection write */ +#define TRICORE_TIN_MPX 4 /* Class 1: protection execute */ +#define TRICORE_TIN_MPP 5 /* Class 1: peripheral access */ +#define TRICORE_TIN_MPN 6 /* Class 1: null address */ +#define TRICORE_TIN_GRWP 7 /* Class 1: global register write */ + +#define TRICORE_TIN_IOPC 1 /* Class 2: illegal opcode */ +#define TRICORE_TIN_UOPC 2 /* Class 2: unimplemented opcode */ +#define TRICORE_TIN_OPD 3 /* Class 2: invalid operand */ +#define TRICORE_TIN_ALN 4 /* Class 2: data address alignment */ +#define TRICORE_TIN_MEM 5 /* Class 2: invalid local memory */ +#define TRICORE_TIN_CSE 6 /* Class 2: coprocessor synchronous */ + +#define TRICORE_TIN_FCD 1 /* Class 3: free context depletion */ +#define TRICORE_TIN_CDO 2 /* Class 3: call depth overflow */ +#define TRICORE_TIN_CDU 3 /* Class 3: call depth underflow */ +#define TRICORE_TIN_FCU 4 /* Class 3: free context underflow */ +#define TRICORE_TIN_CSU 5 /* Class 3: call stack underflow */ +#define TRICORE_TIN_CTYP 6 /* Class 3: context type error */ +#define TRICORE_TIN_NEST 7 /* Class 3: nesting error */ + +#define TRICORE_TIN_PSE 1 /* Class 4: program fetch synchronous */ +#define TRICORE_TIN_DSE 2 /* Class 4: data access synchronous */ +#define TRICORE_TIN_DAE 3 /* Class 4: data access asynchronous */ +#define TRICORE_TIN_CAE 4 /* Class 4: coprocessor asynchronous */ +#define TRICORE_TIN_PIE 5 /* Class 4: program memory integrity */ +#define TRICORE_TIN_DIE 6 /* Class 4: data memory integrity */ +#define TRICORE_TIN_TAE 7 /* Class 4: temporal asynchronous */ + +#define TRICORE_TIN_OVF 1 /* Class 5: arithmetic overflow */ +#define TRICORE_TIN_SOVF 2 /* Class 5: sticky overflow */ + +/* The trap vectors enter tricore_trapcall() with jli, return with ji */ + +#ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING +# define tricore_trap_return() __asm__ volatile ("ji a11" : : : "a11") +#else +# define tricore_trap_return() __asm__ volatile ("ji %a11") +#endif -/* Bus trap hook for safety test modules (e.g., BusMonTst). */ +/* Smallest FCU pool: two CSAs for the trapped context, the rest for the + * panic path. + */ -static tricore_bustrap_hook_t g_bustrap_hook; +#define TRICORE_FCU_CSA_MINNUM 20 + +/* Panic message of a trap, "Trap c=<class> t=<TIN>" */ + +#define TRICORE_TRAP_MSG_LEN 24 /**************************************************************************** - * Private Functions + * Private Types ****************************************************************************/ -static void tricore_trapinfo(volatile void *trap) -{ - IfxCpu_Trap *ctrap = (IfxCpu_Trap *)trap; +/* Last trap and the trap status registers, for the coredump */ - g_trapinfo.tCpu = ctrap->tCpu; - g_trapinfo.tClass = ctrap->tClass; - g_trapinfo.tId = ctrap->tId; - g_trapinfo.tAddr = ctrap->tAddr; -} +struct tricore_trapinfo_s +{ + struct tricore_trap_s trap; + uint32_t pstr; /* Program synchronous trap status */ + uint32_t dstr; /* Data synchronous trap status */ + uint32_t datr; /* Data asynchronous trap */ + uint32_t deadd; /* Data error address */ +}; /**************************************************************************** - * Public Functions + * Private Data ****************************************************************************/ -/**************************************************************************** - * Name: tricore_bustrap_register_hook - * - * Description: - * Register a hook function for bus trap handling. This allows safety test - * modules (e.g., BusMonTst) to intercept and handle expected bus errors - * during self-tests without triggering a system panic. - * - * Input Parameters: - * hook - The hook function to register, or NULL to unregister - * - * Returned Value: - * None - * - ****************************************************************************/ +static struct tricore_trapinfo_s g_trapinfo; -void tricore_bustrap_register_hook(tricore_bustrap_hook_t hook) -{ - g_bustrap_hook = hook; -} +/* FCU pool, also read by tricore_fcu_entry in tricore_vectors.S/.asm */ -int weak_function tricore_nmitrap(uint32_t tid, void *context, void *arg) -{ - _alert("PANIC!!! NMI Trap:\n"); - _alert("\tClass %d TID: %d regs: %p\n", - IfxCpu_Trap_Class_nonMaskableInterrupt, tid, context); +uintptr_t *g_tricore_fcu_pool; +static size_t g_tricore_fcu_num; - up_irq_save(); - PANIC_WITH_REGS("panic", context); - return OK; -} +/* One CSA more than needed, so the start can be aligned to 64 bytes at run + * time; not every toolchain honours a 64-byte alignment request here. + */ -int tricore_mmutrap(uint32_t tid, void *context, void *arg) -{ - _alert("PANIC!!! MMU Trap:\n"); - _alert("\tClass %d TID: %" PRId32 " regs: %p\n", - IfxCpu_Trap_Class_memoryManagement, - tid, context); +#if CONFIG_TRICORE_FCU_CSA_NUM > 0 +static uintptr_t +g_fcu_csa[(CONFIG_TRICORE_FCU_CSA_NUM + 1) * TC_CONTEXT_REGS]; Review Comment: what about keep ptr, not define buffer in arch level, let chip alloc or define them ########## arch/tricore/src/common/gnu/tricore_vectors.S: ########## @@ -0,0 +1,153 @@ +/**************************************************************************** + * arch/tricore/src/common/gnu/tricore_vectors.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Trap vector table, one per core. BTV points at the table of the core in + * use; the linker script keeps the .traptab_cpuN section of that core. + * + * Each 32-byte slot saves the lower context and enters the common trap + * entry with the trap class in %d5; the hardware has put the TIN in %d15 + * and the trap return address in %a11. The entry builds a struct + * tricore_trap_s on the stack and enters the handler with jli, so the + * handler sees PCXI pointing at the lower context of the trapped code. + * The handler returns with ji %a11, then the entry restores the lower + * context and returns from the trap. + * + * Context management traps go through tricore_ctx_entry first: on a free + * context list underflow (FCU, TIN 4) there is no free CSA, so svlcx + * cannot run. tricore_fcu_entry then saves the trapped context into the + * pool registered with tricore_fcu_register_pool() and continues in + * tricore_fcu_recover(). The saved %a4 is lost, as the entry uses it, and + * so is %sp when the trap switched to the interrupt stack. Without a pool + * the core stops in tricore_fcu_entry. + * + * The interrupt vector, one per core, saves the lower context and enters + * tricore_doirq the same way. The startup code sets the priority bits + * of BIV, so every interrupt priority enters this one vector. + * + * tasking/tricore_vectors.asm is the same code in the TASKING syntax. + ****************************************************************************/ + +#include <arch/csfr.h> + + .macro TRAPSLOT cls, entry + svlcx + mov %d5, \cls + j \entry + .p2align 5 + .endm + + .macro TRAPJUMP entry + j \entry + .p2align 5 + .endm + + .macro TRAPTAB cpu + .section .traptab_cpu\cpu, "ax", %progbits + .p2align 8 + .global tricore_trap_vectors_cpu\cpu +tricore_trap_vectors_cpu\cpu: + TRAPSLOT 0, tricore_trap_entry + TRAPSLOT 1, tricore_trap_entry + TRAPSLOT 2, tricore_trap_entry + TRAPJUMP tricore_ctx_entry + TRAPSLOT 4, tricore_trap_entry + TRAPSLOT 5, tricore_trap_entry + TRAPSLOT 6, tricore_syscall_entry + TRAPSLOT 7, tricore_trap_entry + .endm + + TRAPTAB 0 + TRAPTAB 1 + TRAPTAB 2 + TRAPTAB 3 + TRAPTAB 4 + TRAPTAB 5 + + .macro INTVEC cpu Review Comment: ditto -- This is an automated message from the Apache Git Service. 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