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commit abf988f2348e39eb77bfba4bce084d9b0827bc79 Author: raiden00pl <[email protected]> AuthorDate: Wed Nov 4 11:28:31 2026 +0100 arch/arm/stm32n6: Enable AXISRAM3-6 before using the stack. The boot ROM enables only AXISRAM1/2. When .bss and the idle stack extend into AXISRAM3, the first stack push in __start or the .bss clear hung the bus. Enable the banks in the naked entry on a temporary stack at the top of AXISRAM2. Assisted-by: Claude:claude-fable-5-1 Signed-off-by: raiden00pl <[email protected]> --- arch/arm/src/stm32n6/hardware/stm32n6xxx_ramcfg.h | 57 +++++++++++++++++++++++ arch/arm/src/stm32n6/stm32_start.c | 36 ++++++++++++++ arch/arm/src/stm32n6/stm32n6xx_rcc.c | 6 +-- 3 files changed, 94 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/stm32n6/hardware/stm32n6xxx_ramcfg.h b/arch/arm/src/stm32n6/hardware/stm32n6xxx_ramcfg.h new file mode 100644 index 00000000000..f7fe57a49c3 --- /dev/null +++ b/arch/arm/src/stm32n6/hardware/stm32n6xxx_ramcfg.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm/src/stm32n6/hardware/stm32n6xxx_ramcfg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_RAMCFG_H +#define __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_RAMCFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32n6xxx_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* AXISRAMn control register, n = 1..6 */ + +#define STM32_RAMCFG_AXISRAM_CR_OFFSET(n) (((n) - 1) * 0x80) + +/* Register Addresses *******************************************************/ + +#define STM32_RAMCFG_AXISRAM_CR(n) (STM32_RAMCFG_BASE + \ + STM32_RAMCFG_AXISRAM_CR_OFFSET(n)) +#define STM32_RAMCFG_AXISRAM3_CR STM32_RAMCFG_AXISRAM_CR(3) +#define STM32_RAMCFG_AXISRAM4_CR STM32_RAMCFG_AXISRAM_CR(4) +#define STM32_RAMCFG_AXISRAM5_CR STM32_RAMCFG_AXISRAM_CR(5) +#define STM32_RAMCFG_AXISRAM6_CR STM32_RAMCFG_AXISRAM_CR(6) + +/* Register Bitfield Definitions ********************************************/ + +/* AXISRAMn control register */ + +#define RAMCFG_CR_SRAMSD (1 << 20) /* Bit 20: SRAM shutdown */ + +#endif /* __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_RAMCFG_H */ diff --git a/arch/arm/src/stm32n6/stm32_start.c b/arch/arm/src/stm32n6/stm32_start.c index ed11571aeb8..a7eef38c55f 100644 --- a/arch/arm/src/stm32n6/stm32_start.c +++ b/arch/arm/src/stm32n6/stm32_start.c @@ -31,6 +31,7 @@ #include <debug.h> #include <nuttx/init.h> +#include <nuttx/macro.h> #include <arch/barriers.h> #include <arch/board/board.h> @@ -42,6 +43,7 @@ #include "stm32_pwr.h" #include "stm32_start.h" #include "hardware/stm32n6xxx_bsec.h" +#include "hardware/stm32n6xxx_ramcfg.h" #include "hardware/stm32n6xxx_syscfg.h" /**************************************************************************** @@ -112,13 +114,47 @@ void __start_c(void) noinstrument_function; * from the vector table, as a hardware reset would, before any * compiler-generated prologue runs. It then tail-calls __start_c. * + * The boot ROM enables only AXISRAM1/2, but .data, .bss and the idle + * stack may extend into AXISRAM3. AXISRAM3-6 are clocked and taken out + * of RAMCFG shutdown here, before anything uses memory. + * ****************************************************************************/ void __attribute__((naked)) noinstrument_function __start(void) { + /* Clear the stack limits, clock all AXISRAM banks and the RAMCFG, clear + * SRAMSD of AXISRAM3-6, then load MSP from the vector table. + */ + __asm__ volatile ("mov r0, #0\n\t" "msr msplim, r0\n\t" "msr psplim, r0\n\t" + "ldr r0, =" STRINGIFY(STM32_RCC_MEMENSR) "\n\t" + "ldr r1, =" STRINGIFY(RCC_MEMENR_ALLAXISRAM | + RCC_MEMENR_CACHEAXIRAMEN) "\n\t" + "str r1, [r0]\n\t" + "ldr r0, =" STRINGIFY(STM32_RCC_AHB2ENSR) "\n\t" + "ldr r1, =" STRINGIFY(RCC_AHB2ENR_RAMCFGEN) "\n\t" + "str r1, [r0]\n\t" + "dsb\n\t" + "ldr r2, =" STRINGIFY(RAMCFG_CR_SRAMSD) "\n\t" + "ldr r0, =" STRINGIFY(STM32_RAMCFG_AXISRAM3_CR) "\n\t" + "ldr r1, [r0]\n\t" + "bic r1, r1, r2\n\t" + "str r1, [r0]\n\t" + "ldr r0, =" STRINGIFY(STM32_RAMCFG_AXISRAM4_CR) "\n\t" + "ldr r1, [r0]\n\t" + "bic r1, r1, r2\n\t" + "str r1, [r0]\n\t" + "ldr r0, =" STRINGIFY(STM32_RAMCFG_AXISRAM5_CR) "\n\t" + "ldr r1, [r0]\n\t" + "bic r1, r1, r2\n\t" + "str r1, [r0]\n\t" + "ldr r0, =" STRINGIFY(STM32_RAMCFG_AXISRAM6_CR) "\n\t" + "ldr r1, [r0]\n\t" + "bic r1, r1, r2\n\t" + "str r1, [r0]\n\t" + "dsb\n\t" "ldr r0, =_vectors\n\t" "ldr r0, [r0]\n\t" "msr msp, r0\n\t" diff --git a/arch/arm/src/stm32n6/stm32n6xx_rcc.c b/arch/arm/src/stm32n6/stm32n6xx_rcc.c index c76ba39ff02..18d9685263d 100644 --- a/arch/arm/src/stm32n6/stm32n6xx_rcc.c +++ b/arch/arm/src/stm32n6/stm32n6xx_rcc.c @@ -71,6 +71,7 @@ #include "stm32_rcc.h" #include "stm32_pwr.h" #include "stm32_gpio.h" +#include "hardware/stm32n6xxx_ramcfg.h" /**************************************************************************** * Pre-processor Definitions @@ -201,11 +202,6 @@ modifyreg32(STM32_RCC_##reg, RCC_##reg##_##field##_MASK, \ STM32_RCC_##reg##_##field) -/* RAMCFG control register of AXISRAMn (n = 1..6) and its shutdown bit */ - -#define STM32_RAMCFG_AXISRAM_CR(n) (STM32_RAMCFG_BASE + ((n) - 1) * 0x80) -#define RAMCFG_CR_SRAMSD (1 << 20) - /**************************************************************************** * Private Functions ****************************************************************************/
