davids5 commented on issue #11594: URL: https://github.com/apache/nuttx/issues/11594#issuecomment-1908274074
> invalidating triggers a sync of the the SRAM to Dcache memory No it is not like that. The invalidate makes the cache lines invalid so the next read will be out to memory (not the cache) and bring in the lines to the cache. If the code is obeying the use case it should not be reading memory before the DMA completion. I suspect you have some overlapping accesses with specific code changes which you can't share. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
