pussuw commented on code in PR #13978: URL: https://github.com/apache/nuttx/pull/13978#discussion_r1793374519
########## arch/arm64/src/common/arm64_hwdebug.c: ########## @@ -0,0 +1,1311 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_hwdebug.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <inttypes.h> +#include <stdint.h> +#include <string.h> +#include <errno.h> +#include <debug.h> +#include <assert.h> +#include <stdint.h> +#include <fcntl.h> +#include <stdio.h> +#include <nuttx/clock.h> +#include <nuttx/arch.h> +#include <nuttx/fs/procfs.h> +#include <nuttx/sched.h> +#include <sys/types.h> +#include <sys/stat.h> + +#include <arch/irq.h> +#include <arch/chip/chip.h> +#include <sched/sched.h> + +#include "arm64_hwdebug.h" +#include "arm64_fatal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define READ_WB_REG_CASE(OFF, N, REG, VAL) \ + case (OFF + N): \ + AARCH64_DBG_READ(N, REG, VAL); \ + break + +#define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ + case (OFF + N): \ + AARCH64_DBG_WRITE(N, REG, VAL); \ + break + +#define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ + READ_WB_REG_CASE(OFF, 0, REG, VAL); \ + READ_WB_REG_CASE(OFF, 1, REG, VAL); \ + READ_WB_REG_CASE(OFF, 2, REG, VAL); \ + READ_WB_REG_CASE(OFF, 3, REG, VAL); \ + READ_WB_REG_CASE(OFF, 4, REG, VAL); \ + READ_WB_REG_CASE(OFF, 5, REG, VAL); \ + READ_WB_REG_CASE(OFF, 6, REG, VAL); \ + READ_WB_REG_CASE(OFF, 7, REG, VAL); \ + READ_WB_REG_CASE(OFF, 8, REG, VAL); \ + READ_WB_REG_CASE(OFF, 9, REG, VAL); \ + READ_WB_REG_CASE(OFF, 10, REG, VAL); \ + READ_WB_REG_CASE(OFF, 11, REG, VAL); \ + READ_WB_REG_CASE(OFF, 12, REG, VAL); \ + READ_WB_REG_CASE(OFF, 13, REG, VAL); \ + READ_WB_REG_CASE(OFF, 14, REG, VAL); \ + READ_WB_REG_CASE(OFF, 15, REG, VAL) + +#define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \ + WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ + WRITE_WB_REG_CASE(OFF, 15, REG, VAL) + +enum hw_breakpoint_ops +{ + HW_BREAKPOINT_INSTALL, + HW_BREAKPOINT_UNINSTALL, + HW_BREAKPOINT_RESTORE +}; + +enum dbg_active_el +{ + DBG_ACTIVE_EL0 = 0, + DBG_ACTIVE_EL1, +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct arm64_breakpoint_context g_cpu_bp_ctx[CONFIG_SMP_NCPUS]; +static struct arm64_breakpoint_context g_cpu_wp_ctx[CONFIG_SMP_NCPUS]; +static struct arm64_debugpoint_slot g_debugpoint_slots[CONFIG_SMP_NCPUS]; + +static int g_mde_ref_count[CONFIG_SMP_NCPUS]; +static int g_kde_ref_count[CONFIG_SMP_NCPUS]; + +static struct list_node g_break_inst_hook_list_el0; +static struct list_node g_break_inst_hook_list_el1; + +static spinlock_t g_debugpoint_slots_lock; +static spinlock_t g_debug_hook_lock; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static uint64_t read_wb_reg(int reg, int n) +{ + uint64_t val = 0; + + switch (reg + n) + { Review Comment: Indent is wrong -- This is an automated message from the Apache Git Service. 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