patacongo commented on a change in pull request #1380:
URL: https://github.com/apache/incubator-nuttx/pull/1380#discussion_r451869346
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File path: arch/arm/src/stm32f7/stm32_tickless.c
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@@ -988,22 +988,31 @@ int up_timer_start(FAR const struct timespec *ts)
}
#endif
+#ifdef CONFIG_SCHED_TICKLESS_ALARM
int up_alarm_start(FAR const struct timespec *ts)
{
uint64_t tm = ((uint64_t)ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec) /
NSEC_PER_TICK;
- uint64_t counter = ((uint64_t)g_tickless.overflow << 32) |
- STM32_TIM_GETCOUNTER(g_tickless.tch);
-
- g_tickless.last_alrm = tm;
+ irqstate_t flags;
- int32_t diff = tm / NSEC_PER_TICK + counter;
+ flags = enter_critical_section();
STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, tm);
stm32_tickless_ackint(g_tickless.channel);
stm32_tickless_enableint(CONFIG_STM32F7_TICKLESS_CHANNEL);
+ g_tickless.pending = true;
+
+ uint64_t counter = ((uint64_t)g_tickless.overflow << 32) |
+ STM32_TIM_GETCOUNTER(g_tickless.tch);
Review comment:
> If an overflow from the LS to MS occurs, the fetched value will be wrong.
I usually do this (which does not require disabling interrupts):
>
> ```
> uint64_t counter;
> uint32_t ms1;
> uint32_t ms2;
> uint32_t ls;
>
> do
> {
> ms1 = get_ms();
> ls = get_ls();
> ms2 = get_ms();
> }
> while (ms1 != ms2);
>
> counter = (ms1 << 32) | ls;
> ```
Well, I didn't notice that the MS part is just a software overflow counter
and not a hardware register. This that case, what I propose here is nonsense.
If interrupts are disabled, not special precautions needs to be taken.
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