fdcavalcanti opened a new pull request, #16533: URL: https://github.com/apache/nuttx/pull/16533
## Summary - **arch/risc-v: decouple common source for Espressif's MCUBoot port** Decouples the NuttX build from the MCUBoot common source on RISC-V Espressif devices. Allows using different branches for each. - **arch/xtensa: decouple common source for Espressif's MCUBoot port** Decouples the NuttX build from the MCUBoot common source on Xtensa devices. Allows using different branches for each. This PR changes MCUBoot build process for Xtensa and RISC-V Espressif devices. No changes on user side or build process. ## Impact - Impact on user: No. - Impact on build: MCUBoot shared the same esp-hal-3rdparty repository as the Nuttx build. It now clones this repository to a different directory so we can have MCUBoot and Nuttx operate in different hal versions. - Impact on hardware: Espressif Xtensa and RISC-V devices: ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C6, ESP32H2. - Impact on documentation: No. - Impact on security: No. - Impact on compatibility: No. ## Testing Testing was done manually in each SoC and also on QEMU when supported. The following example is shown in QEMU. ### Building - ./tools/configure.sh esp32c3-generic:mcuboot_nsh - make bootloader - Enable CONFIG_ESPRESSIF_MERGE_BINS - make ESPTOOL_BINDIR=./ Those steps should build MCUBoot and NuttX binaries, merging both at the end. ### Running Run QEMU using: `qemu-system-riscv32 -nographic -icount 3 -machine esp32c3 -drive file=nuttx.merged.bin,if=mtd,format=raw` ### Results Boot proceeds normally. ``` Adding SPI flash device ESP-ROM:esp32c3-api1-20210207 Build:Feb 7 2021 rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT) SPIWP:0xee mode:DIO, clock div:1 load:0x3fcd89a8,len:0x183c load:0x403c7000,len:0x24c8 load:0x403d0000,len:0x23ac entry 0x403d2356 [esp32c3] [INF] *** Booting MCUboot build v2.2.0-rc1 *** [esp32c3] [INF] [boot] chip revision: v0.3 [esp32c3] [INF] [boot.esp32c3] SPI Speed : 80MHz [esp32c3] [INF] [boot.esp32c3] SPI Mode : SLOW READ [esp32c3] [INF] [boot.esp32c3] SPI Flash Size : 4MB [esp32c3] [INF] [boot] Enabling RNG early entropy source... [esp32c3] [INF] Primary image: magic=good, swap_type=0x1, copy_done=0x3, image_ok=0x1 [esp32c3] [INF] Scratch: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 [esp32c3] [INF] Boot source: primary slot [esp32c3] [INF] Image index: 0, Swap type: none [esp32c3] [INF] Disabling RNG early entropy source... [esp32c3] [INF] br_image_off = 0x10000 [esp32c3] [INF] ih_hdr_size = 0x20 [esp32c3] [INF] Loading image 0 - slot 0 from flash, area id: 1 [esp32c3] [INF] DRAM segment: start=0x12b56, size=0x570, vaddr=0x3fc82ae0 [esp32c3] [INF] IRAM segment: start=0x10080, size=0x2ad6, vaddr=0x40380000 [esp32c3] [INF] RTC_IRAM segment: paddr=0004af30h, vaddr=50000000h, size=00010h ( 16) load [esp32c3] [INF] start=0x403828f6 rtc_init(dbg): not burn core voltage in efuse or burn wrong voltage value in chip version: 03 NuttShell (NSH) NuttX-10.4.0 nsh> ``` -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
