This is an automated email from the ASF dual-hosted git repository. acassis pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 206d82440e72cad269f0d1456f54b96a508f0e00 Author: raiden00pl <[email protected]> AuthorDate: Sun Oct 11 16:25:13 2026 +0200 arch/arm: enable WWDG clock on STM32C0 and STM32G0 The WWDG driver expects the RCC initialization to enable the WWDG clock, but STM32C0 and STM32G0 never set WWDGEN, so the WWDG was not clocked. Enable it with CONFIG_STM32_WWDG (RCC_APBENR1 bit 11). Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/stm32c0/hardware/stm32_rcc.h | 3 ++- arch/arm/src/stm32c0/stm32c0_rcc.c | 6 ++++++ arch/arm/src/stm32g0/hardware/stm32_rcc.h | 4 +++- arch/arm/src/stm32g0/stm32g0_rcc.c | 6 ++++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32c0/hardware/stm32_rcc.h b/arch/arm/src/stm32c0/hardware/stm32_rcc.h index 5389984e441..a9d644fa0c5 100644 --- a/arch/arm/src/stm32c0/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32c0/hardware/stm32_rcc.h @@ -284,7 +284,8 @@ #define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 clock enable */ #define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 clock enable */ - /* Bits 2-11: Reserved */ + /* Bits 2-10: Reserved */ +#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */ #define RCC_APB1ENR_FDCANEN (1 << 12) /* Bit 12: FDCAN clock enable */ #define RCC_APB1ENR_USBEN (1 << 13) /* Bit 13: USB clock enable */ #define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */ diff --git a/arch/arm/src/stm32c0/stm32c0_rcc.c b/arch/arm/src/stm32c0/stm32c0_rcc.c index 5ef674dc583..066b4a4ee2b 100644 --- a/arch/arm/src/stm32c0/stm32c0_rcc.c +++ b/arch/arm/src/stm32c0/stm32c0_rcc.c @@ -183,6 +183,12 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_FDCANEN; #endif +#ifdef CONFIG_STM32_WWDG + /* Window watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + #ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ diff --git a/arch/arm/src/stm32g0/hardware/stm32_rcc.h b/arch/arm/src/stm32g0/hardware/stm32_rcc.h index 68490521c1a..53112d367be 100644 --- a/arch/arm/src/stm32g0/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32g0/hardware/stm32_rcc.h @@ -285,7 +285,9 @@ /* Bits 2-3: Reserved */ #define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 enable */ #define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 enable */ - /* Bits 6-12: Reserved */ + /* Bits 6-10: Reserved */ +#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog enable */ + /* Bit 12: Reserved */ #define RCC_APB1ENR_USBEN (1 << 13) /* Bit 13: USB enable */ #define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 enable */ /* Bit 15: Reserved */ diff --git a/arch/arm/src/stm32g0/stm32g0_rcc.c b/arch/arm/src/stm32g0/stm32g0_rcc.c index 5a90665f868..0bee1359cc9 100644 --- a/arch/arm/src/stm32g0/stm32g0_rcc.c +++ b/arch/arm/src/stm32g0/stm32g0_rcc.c @@ -211,6 +211,12 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_USBEN; #endif +#ifdef CONFIG_STM32_WWDG + /* Window watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + #ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */
