no1wudi commented on a change in pull request #5192:
URL: https://github.com/apache/incubator-nuttx/pull/5192#discussion_r780624976
##########
File path: arch/risc-v/include/common/irq.h
##########
@@ -121,7 +121,13 @@
#define INT_XCPT_REGS 33
#endif
-#define INT_XCPT_SIZE (8 * INT_XCPT_REGS)
+#ifdef CONFIG_ARCH_RV32
+#define INT_REG_SIZE 4
+#else
+#define INT_REG_SIZE 8
+#endif
Review comment:
Can't do this since uintptr_t is invalid in assembly.
##########
File path: arch/risc-v/src/common/riscv_schedulesigaction.c
##########
@@ -37,6 +37,18 @@
#include "riscv_internal.h"
#include "riscv_arch.h"
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Format output with register width and hex */
+
+#ifdef CONFIG_ARCH_RV32
+# define PRIxREG "%08"PRIxPTR
Review comment:
Done
##########
File path: arch/risc-v/src/fe310/fe310_irq_dispatch.c
##########
@@ -52,10 +52,10 @@ volatile uint32_t * g_current_regs;
* fe310_dispatch_irq
****************************************************************************/
-void *fe310_dispatch_irq(uint32_t vector, uint32_t *regs)
+void *fe310_dispatch_irq(uint32_t vector, uintptr_t *regs)
{
uint32_t irq = (vector >> 27) | (vector & 0xf);
- uint32_t *mepc = regs;
+ uint32_t *mepc = (uint32_t *)regs;
Review comment:
Yes, all of these can be replaced by uintptr_t
##########
File path: arch/risc-v/src/common/riscv_fault.c
##########
@@ -54,61 +66,61 @@
*
****************************************************************************/
-void up_fault(int irq, uint64_t *regs)
+void up_fault(int irq, uintptr_t *regs)
{
CURRENT_REGS = regs;
- _alert("EPC:%016" PRIx64 "\n",
+ _alert("EPC:%0" PRIxREG "\n",
Review comment:
Done
##########
File path: arch/risc-v/src/qemu-rv32/qemu_rv32_head.S
##########
@@ -105,21 +105,6 @@ exception_common:
sw x30, 30*4(sp) /* t5 */
sw x31, 31*4(sp) /* t6 */
-#if defined(INT_XCPT_REGS) && INT_XCPT_REGS >= 39
- csrr x28, 0x7b0
- csrr x29, 0x7b1
- csrr x30, 0x7b2
- sw x28, 33*4(sp)
- sw x29, 34*4(sp)
- sw x30, 35*4(sp)
- csrr x28, 0x7b4
- csrr x29, 0x7b5
- csrr x30, 0x7b6
- sw x28, 36*4(sp)
- sw x29, 37*4(sp)
- sw x30, 38*4(sp)
-#endif
-
Review comment:
It's only works with RV32M1 chips with customized toolchain,
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