pussuw commented on code in PR #6162: URL: https://github.com/apache/incubator-nuttx/pull/6162#discussion_r859834307
########## arch/risc-v/src/common/riscv_pmp.c: ########## @@ -600,9 +600,14 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr, # error "XLEN of risc-v not supported" # endif - /* fence is needed when page-based virtual memory is implemented */ +#ifdef CONFIG_ARCH_HAVE_S_MODE Review Comment: Yes you are absolutely correct that the user level ISA does not mention S as it is part of privileged mode ISA. Table 3.2 lists user + privileged mode encodings both. Using `CONFIG_ARCH_HAVE_S_MODE` here is totally fine, even though the flag does not really indicate chip capabilities right now (I assume mpfs is not the only risc-v target that has S-mode chip level support). Further reading of the privileged spec. would actually indicate that when address translations are not used, PMP does not need the sfence.vma flush either (which makes sense). _Clarified that bare S-mode need not support the SFENCE.VMA instruction._ -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
