cwespressif commented on code in PR #10625:
URL: https://github.com/apache/nuttx/pull/10625#discussion_r1325830513
##########
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c:
##########
@@ -170,6 +199,88 @@ enum core_clock_e
CORE_CLOCK_240M = 3
};
+/****************************************************************************
+ * Private Functions Prototypes
+ ****************************************************************************/
+
+static void IRAM_ATTR set_psram_clock(uint8_t spi_num, uint32_t freqdiv);
+static void IRAM_ATTR set_flash_clock(uint8_t spi_num, uint32_t freqdiv);
+#if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING
+static void init_spi1_for_tuning(bool is_flash);
+static uint32_t get_dummy(void);
+static void set_flash_extra_dummy(uint8_t spi_num, uint8_t extra_dummy);
+static void set_psram_extra_dummy(uint8_t spi_num, uint8_t extra_dummy);
+static void set_flash_din_mode_num(uint8_t spi_num, uint8_t din_mode,
+ uint8_t din_num);
+static void set_psram_din_mode_num(uint8_t spi_num, uint8_t din_mode,
+ uint8_t din_num);
+#if ESP32S3_SPI_TIMING_FLASH_TUNING
+static void config_flash_read_data(uint8_t *buf, uint32_t addr,
+ uint32_t len);
+static void config_flash_set_tuning_regs(const tuning_param_s *params);
+static void get_flash_tuning_configs(tuning_config_s *config);
+#endif
+#if ESP32S3_SPI_TIMING_PSRAM_TUNING
+static void psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len);
+static void psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len);
+static void config_psram_read_write_data(uint8_t *buf, uint32_t addr,
+ uint32_t len, bool is_read);
+static void get_psram_tuning_configs(tuning_config_s *config);
+static void config_psram_set_tuning_regs(const tuning_param_s *params);
+#endif
+static void sweep_for_success_sample_points(const uint8_t *reference_data,
+ const tuning_config_s *config, bool is_flash, uint8_t *out_array);
+static void find_max_consecutive_success_points(uint8_t *array,
+ uint32_t size, uint32_t *out_length, uint32_t *out_end_index);
+#if MSPI_TIMING_FLASH_STR_MODE || MSPI_TIMING_PSRAM_STR_MODE
+static uint32_t select_best_tuning_config_str(tuning_config_s *config,
+ uint32_t consecutive_length, uint32_t end);
+#endif
+#if MSPI_TIMING_FLASH_DTR_MODE || MSPI_TIMING_PSRAM_DTR_MODE
+static uint32_t select_best_tuning_config_dtr(tuning_config_s *config,
+ uint32_t consecutive_length, uint32_t end);
+#endif
+static void select_best_tuning_config(tuning_config_s *config,
+ uint32_t consecutive_length, uint32_t end,
+ const uint8_t *reference_data, bool is_flash);
+static void set_timing_tuning_regs(bool control_spi1);
+static void clear_timing_tuning_regs(bool control_spi1);
+static void do_tuning(const uint8_t *reference_data,
+ tuning_config_s *timing_config, bool is_flash);
+#endif
+
+/****************************************************************************
+ * Extern Functions declaration
+ ****************************************************************************/
+
+#if CONFIG_ESP32S3_SPIRAM_MODE_QUAD
+extern void psram_exec_cmd(int spi_num, int mode,
+ uint32_t cmd, int cmd_bit_len,
+ uint32_t addr, int addr_bit_len,
+ int dummy_bits, uint8_t *mosi_data,
+ int mosi_bit_len, uint8_t *miso_data,
+ int miso_bit_len, uint32_t cs_mask,
+ bool is_write_erase_operation);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING
+#if CONFIG_ESP32S3_SPIRAM_MODE_QUAD
+static uint8_t g_psram_extra_dummy;
+#endif
+static uint8_t g_flash_extra_dummy[2] =
+ {
+ NOT_INIT_INT,
+ NOT_INIT_INT
+ };
Review Comment:
Done
##########
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c:
##########
@@ -238,129 +349,1232 @@ static void IRAM_ATTR set_flash_clock(uint8_t spi_num,
uint32_t freqdiv)
}
}
+#if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING
+
/****************************************************************************
- * Public Functions
+ * Name: init_spi1_for_tuning
+ *
+ * Description:
+ * Initialize SPI1 for timing tuning.
+ *
+ * Input Parameters:
+ * is_flash - is flash or not
+ *
+ * Returned Value:
+ * None.
+ *
****************************************************************************/
+static void init_spi1_for_tuning(bool is_flash)
+{
+ /* Set SPI1 core clock. SPI0 and SPI1 share the register for core clock.
+ * So we only set SPI0 here.
+ */
+
+ REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(0),
+ SPI_MEM_CORE_CLK_SEL,
+ DEFAULT_CORE_CLK_REG);
+
+ /* Set SPI1 module clock as required */
+
+ if (is_flash)
+ {
+ set_flash_clock(1, FLASH_CLOCK_DIVIDER);
+
+ /* Enable Flash HCLK */
+
+ REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CLK_ENA);
+ }
+ else
+ {
+ /* We use SPI1 Flash to tune PSRAM, PSRAM timing related regs
+ * do nothing on SPI1
+ */
+
+ set_flash_clock(1, PSRAM_CLOCK_DIVIDER);
+
+ /* Enable PSRAM HCLK */
+
+ REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(0),
+ SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
+ }
+}
+
/****************************************************************************
- * Name: esp32s3_spi_timing_set_pin_drive_strength
+ * Name: get_dummy
*
* Description:
- * Make SPI all GPIO strength to be 3 under default clock.
+ * Get dummy cycle length
*
* Input Parameters:
* None
*
* Returned Value:
+ * Dummy cycle length.
+ *
+ ****************************************************************************/
+
+static uint32_t get_dummy(void)
+{
+ uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
+ if (ctrl_reg & MSPI_TIMING_LL_FLASH_OCT_MASK)
+ {
+ DEBUGASSERT(0);
Review Comment:
Done
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