cwespressif commented on code in PR #10625:
URL: https://github.com/apache/nuttx/pull/10625#discussion_r1325831831
##########
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c:
##########
@@ -238,129 +349,1232 @@ static void IRAM_ATTR set_flash_clock(uint8_t spi_num,
uint32_t freqdiv)
}
}
+#if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING
+
/****************************************************************************
- * Public Functions
+ * Name: init_spi1_for_tuning
+ *
+ * Description:
+ * Initialize SPI1 for timing tuning.
+ *
+ * Input Parameters:
+ * is_flash - is flash or not
+ *
+ * Returned Value:
+ * None.
+ *
****************************************************************************/
+static void init_spi1_for_tuning(bool is_flash)
+{
+ /* Set SPI1 core clock. SPI0 and SPI1 share the register for core clock.
+ * So we only set SPI0 here.
+ */
+
+ REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(0),
+ SPI_MEM_CORE_CLK_SEL,
+ DEFAULT_CORE_CLK_REG);
+
+ /* Set SPI1 module clock as required */
+
+ if (is_flash)
+ {
+ set_flash_clock(1, FLASH_CLOCK_DIVIDER);
+
+ /* Enable Flash HCLK */
+
+ REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CLK_ENA);
+ }
+ else
+ {
+ /* We use SPI1 Flash to tune PSRAM, PSRAM timing related regs
+ * do nothing on SPI1
+ */
+
+ set_flash_clock(1, PSRAM_CLOCK_DIVIDER);
+
+ /* Enable PSRAM HCLK */
+
+ REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(0),
+ SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
+ }
+}
+
/****************************************************************************
- * Name: esp32s3_spi_timing_set_pin_drive_strength
+ * Name: get_dummy
*
* Description:
- * Make SPI all GPIO strength to be 3 under default clock.
+ * Get dummy cycle length
*
* Input Parameters:
* None
*
* Returned Value:
+ * Dummy cycle length.
+ *
+ ****************************************************************************/
+
+static uint32_t get_dummy(void)
+{
+ uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
+ if (ctrl_reg & MSPI_TIMING_LL_FLASH_OCT_MASK)
+ {
+ DEBUGASSERT(0);
+ return 0;
+ }
+
+#if ESP32S3_SPI_FLASH_HPM_ENABLE
+ /* HPM is not enabled */
+
+ DEBUGASSERT();
+ return 0;
+#endif
+ switch (ctrl_reg & MSPI_TIMING_LL_FLASH_QUAD_MASK)
+ {
+ case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
+ return SPI1_R_QIO_DUMMY_CYCLELEN;
+ case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
+ return SPI1_R_DIO_DUMMY_CYCLELEN;
+ case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
+ case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
+ case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
+ return SPI1_R_FAST_DUMMY_CYCLELEN;
+ default:
+ DEBUGASSERT(0);
+ return 0;
+ }
+}
+
+/****************************************************************************
+ * Name: set_flash_extra_dummy
+ *
+ * Description:
+ * Set MSPI Flash extra dummy
+ *
+ * Input Parameters:
+ * spi_num - SPI0 / 1
+ * extra_dummy - extra dummy
+ *
+ * Returned Value:
* None.
*
****************************************************************************/
-void esp32s3_spi_timing_set_pin_drive_strength(void)
+static void set_flash_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
{
- const uint32_t regs[] =
+#ifdef CONFIG_ESP32S3_FLASH_MODE_OCT
+ if (extra_dummy > 0)
{
- IO_MUX_GPIO27_REG,
- IO_MUX_GPIO28_REG,
- IO_MUX_GPIO31_REG,
- IO_MUX_GPIO32_REG,
- IO_MUX_GPIO33_REG,
- IO_MUX_GPIO34_REG,
- IO_MUX_GPIO35_REG,
- IO_MUX_GPIO36_REG,
- IO_MUX_GPIO37_REG
- };
+ SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num),
+ SPI_MEM_TIMING_CALI_M);
+ SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num),
+ SPI_MEM_EXTRA_DUMMY_CYCLELEN_V,
+ extra_dummy,
+ SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
+ }
+ else
+ {
+ CLEAR_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num),
+ SPI_MEM_TIMING_CALI_M);
+ SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num),
+ SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0,
+ SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
+ }
- /* Set default clock */
+ return;
+#endif
+ if (g_flash_extra_dummy[spi_num] == NOT_INIT_INT)
+ {
+ g_flash_extra_dummy[spi_num] = g_spiflash_dummy_len_plus[spi_num];
+ }
- SET_PERI_REG_MASK(SPI_MEM_DATE_REG(0), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
- REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3);
- REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, 3);
+ g_spiflash_dummy_len_plus[spi_num] = g_flash_extra_dummy[(int)spi_num] +
+ extra_dummy;
- /* Set default mspi d0 ~ d7, dqs pin drive strength */
+ /* Only Quad Flash will run into this branch. */
- for (int i = 0; i < nitems(regs); i++)
+ uint32_t dummy = get_dummy();
+
+ /* Set MSPI Quad Flash dummy */
+
+ SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_DUMMY);
+ SET_PERI_REG_BITS(SPI_MEM_USER1_REG(spi_num), SPI_MEM_USR_DUMMY_CYCLELEN_V,
+ dummy + g_spiflash_dummy_len_plus[spi_num], SPI_MEM_USR_DUMMY_CYCLELEN_S);
Review Comment:
Done
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: [email protected]
For queries about this service, please contact Infrastructure at:
[email protected]
