cwespressif commented on code in PR #10625:
URL: https://github.com/apache/nuttx/pull/10625#discussion_r1325831581
##########
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c:
##########
@@ -238,129 +349,1232 @@ static void IRAM_ATTR set_flash_clock(uint8_t spi_num,
uint32_t freqdiv)
}
}
+#if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING
+
/****************************************************************************
- * Public Functions
+ * Name: init_spi1_for_tuning
+ *
+ * Description:
+ * Initialize SPI1 for timing tuning.
+ *
+ * Input Parameters:
+ * is_flash - is flash or not
+ *
+ * Returned Value:
+ * None.
+ *
****************************************************************************/
+static void init_spi1_for_tuning(bool is_flash)
+{
+ /* Set SPI1 core clock. SPI0 and SPI1 share the register for core clock.
+ * So we only set SPI0 here.
+ */
+
+ REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(0),
+ SPI_MEM_CORE_CLK_SEL,
+ DEFAULT_CORE_CLK_REG);
+
+ /* Set SPI1 module clock as required */
+
+ if (is_flash)
+ {
+ set_flash_clock(1, FLASH_CLOCK_DIVIDER);
+
+ /* Enable Flash HCLK */
+
+ REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CLK_ENA);
+ }
+ else
+ {
+ /* We use SPI1 Flash to tune PSRAM, PSRAM timing related regs
+ * do nothing on SPI1
+ */
+
+ set_flash_clock(1, PSRAM_CLOCK_DIVIDER);
+
+ /* Enable PSRAM HCLK */
+
+ REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(0),
+ SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
+ }
+}
+
/****************************************************************************
- * Name: esp32s3_spi_timing_set_pin_drive_strength
+ * Name: get_dummy
*
* Description:
- * Make SPI all GPIO strength to be 3 under default clock.
+ * Get dummy cycle length
*
* Input Parameters:
* None
*
* Returned Value:
+ * Dummy cycle length.
+ *
+ ****************************************************************************/
+
+static uint32_t get_dummy(void)
+{
+ uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
+ if (ctrl_reg & MSPI_TIMING_LL_FLASH_OCT_MASK)
+ {
+ DEBUGASSERT(0);
+ return 0;
+ }
+
+#if ESP32S3_SPI_FLASH_HPM_ENABLE
+ /* HPM is not enabled */
+
+ DEBUGASSERT();
+ return 0;
Review Comment:
Yes, it has been removed, this function has not been implemented yet.
##########
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c:
##########
@@ -238,129 +349,1232 @@ static void IRAM_ATTR set_flash_clock(uint8_t spi_num,
uint32_t freqdiv)
}
}
+#if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING
+
/****************************************************************************
- * Public Functions
+ * Name: init_spi1_for_tuning
+ *
+ * Description:
+ * Initialize SPI1 for timing tuning.
+ *
+ * Input Parameters:
+ * is_flash - is flash or not
+ *
+ * Returned Value:
+ * None.
+ *
****************************************************************************/
+static void init_spi1_for_tuning(bool is_flash)
+{
+ /* Set SPI1 core clock. SPI0 and SPI1 share the register for core clock.
+ * So we only set SPI0 here.
+ */
+
+ REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(0),
+ SPI_MEM_CORE_CLK_SEL,
+ DEFAULT_CORE_CLK_REG);
+
+ /* Set SPI1 module clock as required */
+
+ if (is_flash)
+ {
+ set_flash_clock(1, FLASH_CLOCK_DIVIDER);
+
+ /* Enable Flash HCLK */
+
+ REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CLK_ENA);
+ }
+ else
+ {
+ /* We use SPI1 Flash to tune PSRAM, PSRAM timing related regs
+ * do nothing on SPI1
+ */
+
+ set_flash_clock(1, PSRAM_CLOCK_DIVIDER);
+
+ /* Enable PSRAM HCLK */
+
+ REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(0),
+ SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
+ }
+}
+
/****************************************************************************
- * Name: esp32s3_spi_timing_set_pin_drive_strength
+ * Name: get_dummy
*
* Description:
- * Make SPI all GPIO strength to be 3 under default clock.
+ * Get dummy cycle length
*
* Input Parameters:
* None
*
* Returned Value:
+ * Dummy cycle length.
+ *
+ ****************************************************************************/
+
+static uint32_t get_dummy(void)
+{
+ uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
+ if (ctrl_reg & MSPI_TIMING_LL_FLASH_OCT_MASK)
+ {
+ DEBUGASSERT(0);
+ return 0;
+ }
+
+#if ESP32S3_SPI_FLASH_HPM_ENABLE
+ /* HPM is not enabled */
+
+ DEBUGASSERT();
+ return 0;
+#endif
+ switch (ctrl_reg & MSPI_TIMING_LL_FLASH_QUAD_MASK)
+ {
+ case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
+ return SPI1_R_QIO_DUMMY_CYCLELEN;
+ case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
+ return SPI1_R_DIO_DUMMY_CYCLELEN;
+ case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
+ case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
+ case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
+ return SPI1_R_FAST_DUMMY_CYCLELEN;
+ default:
+ DEBUGASSERT(0);
Review Comment:
Done
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