JieGH opened a new issue, #17625:
URL: https://github.com/apache/tvm/issues/17625
# TVM/LLVM sets RISC-V VLEN to 128 bits instead of 256 on Banana Pi K1
## Expected Behavior
I have a vecter-based TVM design that shows poor performance against C
implementation, 1/4 of performance approx.
The LLVM warns VLEN to be set as default 128 bits, but the Banana Pi should
uses 256 bits instead.
TVM and LLVM should correctly detect and utilize a vector length (VLEN) of
256 bits on the Banana Pi K1 board.
## Actual Behavior
- The board reports `VLEN=256` when querying via `csrr a4, vlenb` in
assembly.
-- The ASM code shows:
```
vector_test_compute_:
.Lfunc_begin1:
.loc 1 0 0
.cfi_startproc
csrr a4, vlenb
srli t0, a4, 1
li a2, 1024
bltu a2, t0, .LBB1_7
.Ltmp107:
addi a2, t0, -1
andi a7, a2, 1024
xori a6, a7, 1024
slli t1, a4, 1
mv a5, a1
mv a3, a0
mv a2, a6
vsetvli a4, zero, e32, m2, ta, ma
```
- However, LLVM outputs a warning: ``src/target/llvm/codegen_llvm.cc:185:
Warning: Set native vector bits to be 128 for riscv64``
- Attempts to override with flags like `-mllvm -riscv-v-vector-bits-min=256
-mllvm -riscv-v-vector-bits-max=256` do not take effect, llvm says it illegal
flags, then it recommend
- ```ValueError: Error when parsing target["mllvm"]: Cannot recognize
'mllvm'. Candidates are: cl-opt, opt-level, fast-math-ninf, fast-math-arcp,
fast-math-nnan, fast-math, fast-math-contract, num-cores, device, libs, tag,
mtriple, host, from_device, target_device_type, fast-math-reassoc, keys, mattr,
fast-math-nsz, model, mabi, mcpu, jit, mfloat-abi. Target creation from string
failed: llvm -jit=orcjit -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+m,+a,+f,+d,+zfh,+v,+c -mllvm -riscv-v-vector-bits-min=256 -mllvm
-riscv-v-vector-bits-max=256```
### Could anyone advice me how can I set the correct vector length to 256
bits? And from your @cbalint13 knowledge of RISCV, could you provide some
advice? Thanks all.
## Environment
```
LLVM version 19.1.3
Optimized build with assertions.
Default target: riscv64-linux-gnu
Host CPU: generic-rv64
Registered Targets:
riscv32 - 32-bit RISC-V
riscv64 - 64-bit RISC-V
TVM: 0.18.0
Linux k1 6.1.15 #1.0.15.1 SMP PREEMPT Sat Sep 7 07:20:18 UTC 2024 riscv64
riscv64 riscv64 GNU/Linux
riscv64-linux-gnu-gcc --version
riscv64-linux-gnu-gcc (Ubuntu 13.2.0-4ubuntu3-bb2) 13.2.0
Copyright (C) 2023 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
```
llvm -jit=orcjit -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+m,+a,+f,+d,+zfh,+v,+c
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