JieGH commented on issue #17625:
URL: https://github.com/apache/tvm/issues/17625#issuecomment-2647652356
Hi @cbalint13, Thanks for the advice. I now have a method for choosing VLEN,
which is using an additional flag:
` tvm.target.Target("llvm -jit=orcjit -mtriple=riscv64 -mcpu=spacemit-x60 -
mattr=+64bit,+m,+a,+f,+d,+c,+zfh,+v,+zvl256b")`
By specifying zvl256b flags, it means enable 'Zvl' (Minimum Vector Length)
256. This indeed has an impact on the execution's performance.
However,
1) the TVM still warns the 128bit sets as default bit length despite the zvl
flags having been enabled and having an impact on performance. I have not yet
run the latest update you posted at Handle vector width (VLEN) for RISCV arches
#17631
2) I searched zvl flags for a given matrix mul problem; I changed the zvl
and measured the performance. The best performance appeared at the vector
length that the chip should not support. For example if I set zvl256b, the
execution takes 491ms to complete, if I set zvl8192b, the execution takes 384
ms to finish, which has over 20% speed up. There are something wrong here.
Any comments on this? Thanks.
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