cbalint13 commented on issue #17625:
URL: https://github.com/apache/tvm/issues/17625#issuecomment-2636471223
Hi @JieGH
Regarding arch specific technical details {CPU: type, variations, features}
TVM relay on LLVM itself (it queries the very library). AFAIK, when its about
RISCV land, there are limited [infos within LLVM
available](https://github.com/topperc/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVProcessors.td),
limited to interest, maintainance, with things mostly coming from SiFive folks.
Let me look and tackle this problem and come up with best way for TVM, here
are some possibilities on my mind:
0. Let me look once again in LLVM what info regarding VLEN can be queried,
and implement such query for the VLEN.
If the LLVM query don't work (cpu variation is not enlisted in LLVM) let's
further override within TVM:
1. Let's also make the flag for TVM like "-riscv-v-vector-bits-min=256" to
work properly (currently TVM hardcode it to 256).
2. Let's also declare the arches in TVM way (spacemit, th1520, C906, etc)
[see
here](https://github.com/apache/tvm/blob/9404fb5a59766d19fb89944c8c4283b44c30977a/python/tvm/target/target.py#L600),
but this requires maintenance on long term.
I believe {0 + 1, 2} can be implemented all together to offer users multiple
ways of control.
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