aasorokiin opened a new pull request #8797: URL: https://github.com/apache/tvm/pull/8797
Proposed changes to VTA require verilator include directory to build module.cc. Background: VTA modification is proposed to support 64/128/256/512 bit AXI data bus. (vta pull request VTA Chisel Wide memory interface. #32) DPI support for those bit widths is implemented using svOpenArrayHandle from Verilator library from svdpi.h . The original implementation of module.cc uses 8/64 bit data type match and doesn't require special handling. Resolves problem: module.cc is compiled into tsim library by TVM. Code contributions to this PR were made by the following individuals (in alphabetical order): @suvadeep89, @stevenmburns, @pasqoc, @adavare, @sjain12intel, @aasorokiin, and @zhenkuny. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
