vegaluisjose commented on a change in pull request #32:
URL: https://github.com/apache/tvm-vta/pull/32#discussion_r700373427
##########
File path: hardware/chisel/src/main/scala/interface/axi/AXI.scala
##########
@@ -211,7 +211,7 @@ class AXIMaster(params: AXIParams) extends AXIBase(params) {
ar.bits.qos := params.qosConst.U
ar.bits.region := params.regionConst.U
ar.bits.size := params.sizeConst.U
- ar.bits.id := params.idConst.U
+ //do not override
Review comment:
btw, what is up with `ar.bits.id` and `w.bits.strb` here? by default the
strobe mask is all ones
##########
File path: hardware/chisel/src/main/scala/shell/VME.scala
##########
@@ -101,12 +152,13 @@ class VMEWriteMaster(implicit p: Parameters) extends
Bundle {
class VMEWriteClient(implicit p: Parameters) extends Bundle {
val dataBits = p(ShellKey).memParams.dataBits
val cmd = Flipped(Decoupled(new VMECmd))
- val data = Flipped(Decoupled(UInt(dataBits.W)))
+ val data = Flipped(Decoupled(new VMEWriteData))
val ack = Output(Bool())
override def cloneType =
- new VMEWriteClient().asInstanceOf[this.type]
+ new VMEWriteClient().asInstanceOf[this.type]
}
+
Review comment:
remove line
##########
File path: hardware/chisel/src/main/scala/shell/VME.scala
##########
@@ -136,68 +188,178 @@ class VMEClient(implicit p: Parameters) extends Bundle {
* This unit multiplexes the memory controller interface for the Core.
Currently,
* it supports single-writer and multiple-reader mode and it is also based on
AXI.
*/
+
Review comment:
remove line
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