aasorokiin commented on a change in pull request #32:
URL: https://github.com/apache/tvm-vta/pull/32#discussion_r700414594
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File path: hardware/chisel/src/main/scala/interface/axi/AXI.scala
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@@ -211,7 +211,7 @@ class AXIMaster(params: AXIParams) extends AXIBase(params) {
ar.bits.qos := params.qosConst.U
ar.bits.region := params.regionConst.U
ar.bits.size := params.sizeConst.U
- ar.bits.id := params.idConst.U
+ //do not override
Review comment:
IMHO, those are not defaults. They were set in setConst. That expected
no change of value.
VME write path did not get changed other than supporting wider data. It was
not identified critical for hiding memory access latency. DE10 config AXI burst
of 16 pulses was short enough to make hiding burst-to-burst read latency
important. Now even 1 pulse bursts can potentially transfer read data without
gaps.
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