vegaluisjose commented on a change in pull request #32:
URL: https://github.com/apache/tvm-vta/pull/32#discussion_r700400454
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File path: hardware/chisel/src/main/scala/interface/axi/AXI.scala
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@@ -211,7 +211,7 @@ class AXIMaster(params: AXIParams) extends AXIBase(params) {
ar.bits.qos := params.qosConst.U
ar.bits.region := params.regionConst.U
ar.bits.size := params.sizeConst.U
- ar.bits.id := params.idConst.U
+ //do not override
Review comment:
Sure but why changing the defaults? Isn't better to let these modules to
customize (override) these values?
Also, if it is done for reads `ar` why it is not done for writes `aw`?
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