aasorokiin commented on a change in pull request #32: URL: https://github.com/apache/tvm-vta/pull/32#discussion_r702037842
########## File path: hardware/chisel/src/test/scala/unittest/SyncQueueTest.scala ########## @@ -0,0 +1,266 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +package unittest + +import chisel3._ +import chisel3.util._ +import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} +import scala.util.Random +import unittest.util._ +import vta.util._ +import vta.util.config._ + +class TestOnePortMem(c: OnePortMem[UInt]) extends PeekPokeTester(c) { + + // write a:0 d:24 + println("-----------------------------") + println("Cycle 0 write 24 to address 0") + poke (c.io.wr_en, 1) + poke (c.io.wr_data, 24) + poke (c.io.ch_en, 1) + poke (c.io.addr, 0) + step(1) + println("-----------------------------") + // read a:0 + println("Cycle 1 read address 0") + poke (c.io.wr_en, 0) + poke (c.io.addr, 0) + poke (c.io.ch_en, 1) + step(1) + println("-----------------------------") + // write a:1 d:99 + println("Cycle 2 write 99 to address 1") + poke (c.io.wr_en, 1) + poke (c.io.wr_data, 99) + poke (c.io.ch_en, 1) + poke (c.io.addr, 1) + // read d:24 + println("Cycle 2 read expect data 24") + expect (c.io.rd_data, 24) + step(1) + println("-----------------------------") + println("Cycle 3 should still read data 24") + poke (c.io.ch_en, 0) + // read d:24 + expect (c.io.rd_data, 24) + step(1) + println("-----------------------------") + println("Cycle 4 read address 0") + poke (c.io.wr_en, 0) + poke (c.io.addr, 0) + poke (c.io.ch_en, 1) + step(1) + println("-----------------------------") + // write a:1 d:99 + poke (c.io.wr_en, 0) + poke (c.io.wr_data, 99) + poke (c.io.ch_en, 0) + poke (c.io.addr, 1) + // read d:24 + println("Cycle 5 read expect data 24") + expect (c.io.rd_data, 24) + step(1) + println("-----------------------------") +} +class Checker(c: SyncQueueTestWrapper[UInt], t: PeekPokeTester[SyncQueueTestWrapper[UInt]]) { + + def bits (bits: Int) = { + t.expect(c.io.tq.deq.bits, bits) + t.expect(c.io.rq.deq.bits, bits) + + } + def ready (bits: Int) = { + t.expect(c.io.tq.enq.ready, bits) + t.expect(c.io.rq.enq.ready, bits) + + } + def valid (bits: Int) = { + t.expect(c.io.tq.deq.valid, bits) + t.expect(c.io.rq.deq.valid, bits) + + } + def status () = { + val rv = t.peek(c.io.rq.enq.ready) + t.expect(c.io.tq.enq.ready, rv) + val rc = t.peek(c.io.rq.count) + t.expect(c.io.tq.count, rc) + val vv = t.peek(c.io.rq.deq.valid) + t.expect(c.io.tq.deq.valid, vv) + if (vv != 0) { + val bv = t.peek(c.io.rq.deq.bits) + t.expect(c.io.tq.deq.bits, bv) + } + t.peek(c.io.rq.count) + t.peek(c.io.tq.count) + } +} +class TestSyncQueueLongRead(c: SyncQueueTestWrapper[UInt]) extends PeekPokeTester(c) { + + val chr = new Checker (c, this) + + def testFillRW(depth: Int) = { + //println(s"-D- run test depth ${depth}") Review comment: fixed in PR ########## File path: hardware/chisel/src/test/scala/unittest/SyncQueueTest.scala ########## @@ -0,0 +1,266 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +package unittest + +import chisel3._ +import chisel3.util._ +import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} +import scala.util.Random +import unittest.util._ +import vta.util._ +import vta.util.config._ + +class TestOnePortMem(c: OnePortMem[UInt]) extends PeekPokeTester(c) { + + // write a:0 d:24 + println("-----------------------------") + println("Cycle 0 write 24 to address 0") + poke (c.io.wr_en, 1) + poke (c.io.wr_data, 24) + poke (c.io.ch_en, 1) + poke (c.io.addr, 0) + step(1) + println("-----------------------------") + // read a:0 + println("Cycle 1 read address 0") + poke (c.io.wr_en, 0) + poke (c.io.addr, 0) + poke (c.io.ch_en, 1) + step(1) + println("-----------------------------") + // write a:1 d:99 + println("Cycle 2 write 99 to address 1") + poke (c.io.wr_en, 1) + poke (c.io.wr_data, 99) + poke (c.io.ch_en, 1) + poke (c.io.addr, 1) + // read d:24 + println("Cycle 2 read expect data 24") + expect (c.io.rd_data, 24) + step(1) + println("-----------------------------") + println("Cycle 3 should still read data 24") + poke (c.io.ch_en, 0) + // read d:24 + expect (c.io.rd_data, 24) + step(1) + println("-----------------------------") + println("Cycle 4 read address 0") + poke (c.io.wr_en, 0) + poke (c.io.addr, 0) + poke (c.io.ch_en, 1) + step(1) + println("-----------------------------") + // write a:1 d:99 + poke (c.io.wr_en, 0) + poke (c.io.wr_data, 99) + poke (c.io.ch_en, 0) + poke (c.io.addr, 1) + // read d:24 + println("Cycle 5 read expect data 24") + expect (c.io.rd_data, 24) + step(1) + println("-----------------------------") +} +class Checker(c: SyncQueueTestWrapper[UInt], t: PeekPokeTester[SyncQueueTestWrapper[UInt]]) { + + def bits (bits: Int) = { + t.expect(c.io.tq.deq.bits, bits) + t.expect(c.io.rq.deq.bits, bits) + + } + def ready (bits: Int) = { + t.expect(c.io.tq.enq.ready, bits) + t.expect(c.io.rq.enq.ready, bits) + + } + def valid (bits: Int) = { + t.expect(c.io.tq.deq.valid, bits) + t.expect(c.io.rq.deq.valid, bits) + + } + def status () = { + val rv = t.peek(c.io.rq.enq.ready) + t.expect(c.io.tq.enq.ready, rv) + val rc = t.peek(c.io.rq.count) + t.expect(c.io.tq.count, rc) + val vv = t.peek(c.io.rq.deq.valid) + t.expect(c.io.tq.deq.valid, vv) + if (vv != 0) { + val bv = t.peek(c.io.rq.deq.bits) + t.expect(c.io.tq.deq.bits, bv) + } + t.peek(c.io.rq.count) + t.peek(c.io.tq.count) + } +} +class TestSyncQueueLongRead(c: SyncQueueTestWrapper[UInt]) extends PeekPokeTester(c) { + + val chr = new Checker (c, this) + + def testFillRW(depth: Int) = { + //println(s"-D- run test depth ${depth}") + val qsize = peek(c.io.tq.count) + require(qsize == 0, s"-F- An empty queue is expected ${qsize}") + + poke (c.io.tq.deq.ready, 0) + poke (c.io.tq.enq.valid, 0) + chr.ready(1) + step(1) + + // fill up to depth + for (i <- 10 until 10 + depth) { + poke (c.io.tq.enq.bits, i) + poke (c.io.tq.enq.valid, 1) + chr.status() + step(1) + + } + // read and write same cycle + for (i <- 30 + depth until 30 + depth * 2) { + poke (c.io.tq.enq.valid, 1) + poke (c.io.tq.deq.ready, 1) + poke (c.io.tq.enq.bits, i) + chr.status() + step(1) + } + // read out + for (i <- 0 until depth + 1) { + poke (c.io.tq.enq.valid, 0) + poke (c.io.tq.deq.ready, 1) + poke (c.io.tq.enq.bits, 99) + chr.status() + step(1) + } + } + for (i <- 1 until 28) { + testFillRW(i) + } +} +class TestSyncQueueWaveRead(c: SyncQueueTestWrapper[UInt]) extends PeekPokeTester(c) { + + val chr = new Checker (c, this) + + def testFillRW(depth: Int) = { + //println(s"-D- run test depth ${depth}") Review comment: fixed in PR ########## File path: hardware/dpi/tsim_device.cc ########## @@ -58,19 +60,25 @@ void VTAHostDPI(dpi8_t* req_valid, resp_valid, resp_value); } -void VTAMemDPI(dpi8_t req_valid, - dpi8_t req_opcode, - dpi8_t req_len, - dpi64_t req_addr, +void VTAMemDPI(dpi8_t rd_req_valid, + dpi8_t rd_req_len, + dpi8_t rd_req_id, Review comment: fixed in PR -- This is an automated message from the Apache Git Service. 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