tmoreau89 commented on a change in pull request #32: URL: https://github.com/apache/tvm-vta/pull/32#discussion_r701575749
########## File path: hardware/chisel/src/main/scala/core/TensorLoadNarrowVME.scala ########## @@ -0,0 +1,740 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +package vta.core + +import scala.math.pow +import scala.math.sqrt + +import chisel3._ +import chisel3.util._ +import vta.util.config._ +import vta.shell._ + + +/** TensorLoad. + * + * Load 1D and 2D tensors from main memory (DRAM) to input/weight + * scratchpads (SRAM). Also, there is support for zero padding, while + * doing the load. + */ +class TensorLoadNarrowVME(tensorType: String = "none", debug: Boolean = false)( + implicit p: Parameters) + extends Module { + val tp = new TensorParams(tensorType) + val mp = p(ShellKey).memParams + val io = IO(new Bundle { + val start = Input(Bool()) + val done = Output(Bool()) + val inst = Input(UInt(INST_BITS.W)) + val baddr = Input(UInt(mp.addrBits.W)) + val vme_rd = new VMEReadMaster + val tensor = new TensorClient(tensorType) + }) + val writePipeLatency = tp.writePipeLatency + + val sIdle :: sBusy :: Nil = + Enum(2) + val state = RegInit(sIdle) + + val isBusy = state === sBusy + + val localDone = Wire(Bool()) + when(io.start) { + state := sBusy + }.elsewhen(localDone) { + state := sIdle + } + + val dec = io.inst.asTypeOf(new MemDecode) + + val vmeDataBitsPipe = RegNext(io.vme_rd.data.bits) + val vmeDataValidPipe = RegNext(io.vme_rd.data.valid, init = false.B) + val vmeDataReadyPipe = RegNext(io.vme_rd.data.ready, init = false.B) + val vmeDataFirePipe = vmeDataValidPipe & vmeDataReadyPipe + + //-------------------------------------- + //--- Generate data load VME command --- + //-------------------------------------- + val vmeCmd = Module (new GenVMECmd(tensorType, debug)) + vmeCmd.io.start := io.start + vmeCmd.io.isBusy := isBusy + vmeCmd.io.inst := io.inst + vmeCmd.io.baddr := io.baddr + vmeCmd.io.vmeCmd <> io.vme_rd.cmd + val readLen = vmeCmd.io.readLen + val commandsDone = vmeCmd.io.done + + // count how many blocks not receved + val blkIdxWdth = log2Ceil(tp.tsSizeRatio * tp.memDepth) // the size of scratchpad in blocks + // Nb of data blocks requestd, not received. TODO: smaller width parameter Review comment: typo -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
