aasorokiin commented on a change in pull request #32:
URL: https://github.com/apache/tvm-vta/pull/32#discussion_r702038035
##########
File path: hardware/dpi/tsim_device.cc
##########
@@ -58,19 +60,25 @@ void VTAHostDPI(dpi8_t* req_valid,
resp_valid, resp_value);
}
-void VTAMemDPI(dpi8_t req_valid,
- dpi8_t req_opcode,
- dpi8_t req_len,
- dpi64_t req_addr,
+void VTAMemDPI(dpi8_t rd_req_valid,
+ dpi8_t rd_req_len,
+ dpi8_t rd_req_id,
+ dpi64_t rd_req_addr,
+ dpi8_t wr_req_valid,
+ dpi8_t wr_req_len,
+ dpi64_t wr_req_addr,
dpi8_t wr_valid,
- dpi64_t wr_value,
+ const svOpenArrayHandle wr_value,
+ dpi64_t wr_strb,
dpi8_t* rd_valid,
- dpi64_t* rd_value,
+ dpi8_t* rd_id,
Review comment:
fixed in PR
##########
File path: hardware/chisel/src/main/scala/core/LoadUop.scala
##########
@@ -67,160 +64,43 @@ class LoadUop(debug: Boolean = false)(implicit p:
Parameters) extends Module {
val vme_rd = new VMEReadMaster
val uop = new UopClient
})
- val numUop = 2 // store two uops per sram word
- val uopBits = p(CoreKey).uopBits
- val uopBytes = uopBits / 8
- val uopDepth = p(CoreKey).uopMemDepth / numUop
- val dec = io.inst.asTypeOf(new MemDecode)
- val raddr = Reg(chiselTypeOf(io.vme_rd.cmd.bits.addr))
- val xcnt = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len))
- val xlen = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len))
- val xrem = Reg(chiselTypeOf(dec.xsize))
- val xsize = (dec.xsize >> log2Ceil(numUop)) + dec.xsize(0) +
(dec.sram_offset % 2.U) - 1.U
- val xmax = (1 << mp.lenBits).U
- val xmax_bytes = ((1 << mp.lenBits) * mp.dataBits / 8).U
+ // force simple load uop implementation be careful if
+ // define simple tensor load
+ val forceSimpleLoadUop = false;
- val dram_even = (dec.dram_offset % 2.U) === 0.U
- val sram_even = (dec.sram_offset % 2.U) === 0.U
- val sizeIsEven = (dec.xsize % 2.U) === 0.U
+ if (forceSimpleLoadUop) {
+ require(mp.dataBits == 64, "-F- Original LoadUop supports only 64 bit
memory data transfer")
- val sIdle :: sReadCmd :: sReadData :: Nil = Enum(3)
- val state = RegInit(sIdle)
+ val loadUop = Module(new LoadUopSimple(debug))
- // control
- switch(state) {
- is(sIdle) {
- when(io.start) {
- state := sReadCmd
- when(xsize < xmax) {
- xlen := xsize
- xrem := 0.U
- }.otherwise {
- xlen := xmax - 1.U
- xrem := xsize - xmax
- }
- }
- }
- is(sReadCmd) {
- when(io.vme_rd.cmd.ready) {
- state := sReadData
- }
- }
- is(sReadData) {
- when(io.vme_rd.data.valid) {
- when(xcnt === xlen) {
- when(xrem === 0.U) {
- state := sIdle
- }.otherwise {
- raddr := raddr + xmax_bytes
- when(xrem < xmax) {
- state := sReadCmd
- xlen := xrem
- xrem := 0.U
- }
- .otherwise {
- state := sReadCmd
- xlen := xmax - 1.U
- xrem := xrem - xmax
- }
- }
- }
- }
- }
- }
+ loadUop.io.start := io.start
+ io.done := loadUop.io.done
+ loadUop.io.baddr := io.baddr
+ loadUop.io.vme_rd <> io.vme_rd
- // read-from-dram
- val maskOffset = VecInit(Seq.fill(M_DRAM_OFFSET_BITS)(true.B)).asUInt
- when(state === sIdle) {
- when(dram_even) {
- raddr := io.baddr | (maskOffset & (dec.dram_offset <<
log2Ceil(uopBytes)))
- }.otherwise {
- raddr := (io.baddr | (maskOffset & (dec.dram_offset <<
log2Ceil(uopBytes)))) - uopBytes.U
- }
- }
+ loadUop.io.dec := io.inst.asTypeOf(new MemDecode)
+ loadUop.io.uop.idx <> io.uop.idx
+ io.uop <> loadUop.io.uop
- io.vme_rd.cmd.valid := state === sReadCmd
- io.vme_rd.cmd.bits.addr := raddr
- io.vme_rd.cmd.bits.len := xlen
+ } else {
+ //println(
Review comment:
fixed in PR
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