[GitHub] [tvm] alter-xp commented on pull request #12534: [Docker][CI][RISC-V] Build riscv-isa-sim (spike) in ci_riscv Docker image to enable RISC-V unit testing

[GitBox]

alter-xp commented on PR #12534:
URL: https://github.com/apache/tvm/pull/12534#issuecomment-1225141228

   @areusch Currently, there is only one Xuantie compiler in ci_riscv. I 
ignored the situation of baremetal before. I can add it in image. But It seems 
better to add it directly to this pr because this PR needs to use it. What do 
you @PhilippvK think?
   
   


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