adstraw opened a new pull request, #13844: URL: https://github.com/apache/tvm/pull/13844
Add software cache management to enable DMA with cache bypass enabled. DMA with cache bypass is an experimental feature requiring software management of the cache. DMA with cache bypass enabled assumes that HexagonBuffer objects are not cached unless explicitly modified by the primfunc. This PR adds cache flush and invalidation after HexagonBuffer allocation with `malloc` or copy with `memcpy` to uphold that assumption. In addition, this PR adds logic to flush and invalidate the cache prior to a DMA with cache bypass enabled when the buffer in question has been modified by the primfunc. The `test_matmul.py` test hits this case by performing layout transforms in global address space ahead of a DMA. CC @csullivan with thanks for providing the test in question. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
