janetsc commented on code in PR #13844:
URL: https://github.com/apache/tvm/pull/13844#discussion_r1088179888
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src/runtime/hexagon/hexagon_buffer.cc:
##########
@@ -49,6 +49,16 @@ struct Allocation {
struct DDRAllocation : public Allocation {
DDRAllocation(size_t nbytes, size_t alignment) : Allocation(nbytes,
alignment) {
int ret = posix_memalign(&data_, alignment, nbytes);
+
+ // The heap used by malloc on Hexagon is always mapped as cacheable. The
heap manager may
+ // not perform cache flush and invalidation on a prior memory free. So, a
subsequent memory
+ // allocation request to the heap manager may allocate memory that resides
in part or in full in
+ // the cache. Hence, we must flush and invalidate the allocation from the
cache to ensure that
+ // DMA with cache bypass enabled will function properly. DMA with cache
bypass enabled assumes
+ // that HexagonBuffer objects are not cached unless explicitly modified by
the primfunc. We must
+ // flush and invalidate after malloc to uphold this assumption.
+ qurt_mem_cache_clean(reinterpret_cast<qurt_addr_t>(data_), nbytes,
+ QURT_MEM_CACHE_FLUSH_INVALIDATE, QURT_MEM_DCACHE);
Review Comment:
Could this be invalidate only, since there is no data copied in this buffer
yet?
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