-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 andre wrote:
This is a hardware feature not a driver software implementation. 128 bits graphic chips would have much much work addressing odd order of bytes boundary (24bits 3 bytes) in memory even worse this would require one more address line switch and additional logic for the RAMDAC to decode pixels colour at an odd boundary de facto reducing decoding speed.On Friday 13 December 2002 18:38, Murray J. Root wrote:To followup myself - according to NVidia docs, 24bpp uses 32bpp, just the high order 8 bits are not used. So the correct calculation is 1600*1200 pixels * 32bpp/8bits_per_byte / (1024*1024 bytes_per_Meg) = 7.3M
I know that is true for the open source drivers but i'm not 100% sure that that is also true for the clsoed ones
If you only do 2 and 4 byte addressing you can complietely avoid using the lower addres line, transfering data with twice and fourth the bandwidth required by single byte addressing.
- -- L�a Gris
() Campagne du ruban texte brut contre les courriels en HTML,
/\ contre les pi�ces jointes Microsoft.
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