On Thu, 5 Nov 2026 03:45:26 GMT, Jatin Bhateja <[email protected]> wrote:
>> Hi All, >> >> x86 AVX-512 targets provides packed shifts for 16, 32, and 64-bit lanes, but >> not for bytes. C2 lowers LShiftVB, RShiftVB, and URShiftVB by widening bytes >> to words, shifting, masking, and packing. That sequence is the byte-shift >> bottleneck. >> >> GFNI **gf2p8affineqb** instruction applies one 8×8 bit matrix to every byte. >> Logical left, logical right, and arithmetic right shifts by 0..7 are fixed >> matrices derived from the identity 0x0102040810204080. >> >> Patch uses this lowering for 128-, 256-, and 512-bit vectors when GFNI is >> available and keeps the existing widen/shift/pack path when GFNI is absent. >> >> Following are the performance numbers of benchmark included with the patch. >> >> System: AMD EPYC 9755 128-Core Processor (Turin) Fixed frequency 2.5Ghz >> >> Baseline:- >> ---------- >> Benchmark (shift) Mode Cnt Score Error >> Units >> ByteShiftBenchmark.ashr128 3 thrpt 2 24994.026 >> ops/us >> ByteShiftBenchmark.ashr256 3 thrpt 2 29289.608 >> ops/us >> ByteShiftBenchmark.ashr512 3 thrpt 2 39944.806 >> ops/us >> ByteShiftBenchmark.autoVecAshr 3 thrpt 2 32592.174 >> ops/us >> ByteShiftBenchmark.autoVecLshl 3 thrpt 2 30668.901 >> ops/us >> ByteShiftBenchmark.lshl128 3 thrpt 2 25247.149 >> ops/us >> ByteShiftBenchmark.lshl256 3 thrpt 2 27345.375 >> ops/us >> ByteShiftBenchmark.lshl512 3 thrpt 2 38500.755 >> ops/us >> ByteShiftBenchmark.lshr128 3 thrpt 2 25081.398 >> ops/us >> ByteShiftBenchmark.lshr256 3 thrpt 2 28272.477 >> ops/us >> ByteShiftBenchmark.lshr512 3 thrpt 2 42186.028 >> ops/us >> >> Withopt:- >> --------- >> Benchmark (shift) Mode Cnt Score Error >> Units >> ByteShiftBenchmark.ashr128 3 thrpt 2 31313.173 >> ops/us >> ByteShiftBenchmark.ashr256 3 thrpt 2 58663.746 >> ops/us >> ByteShiftBenchmark.ashr512 3 thrpt 2 50472.509 >> ops/us >> ByteShiftBenchmark.autoVecAshr 3 thrpt 2 44965.109 >> ops/us >> ByteShiftBenchmark.autoVecLshl 3 thrpt 2 46304.515 >> ops/us >> ByteShiftBenchmark.lshl128 3 thrpt 2 28849.321 >> ops/us >> ByteShiftBenchmark.lshl256 3 thrpt 2 40492.534 >> ops/us >> ByteShiftBenchmark.lshl512 3 t... > > Jatin Bhateja has refreshed the contents of this pull request, and previous > commits have been removed. The incremental views will show differences > compared to the previous content of the PR. The pull request contains one new > commit since the last revision: > > Review comments resolution src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp line 1431: > 1429: } > 1430: movdl(rtmp, shift); > 1431: andl(rtmp, 31); Forgot one minor thing: masking off upper bits is redundant here, the mask is already applied to the shift operand. And if you drop it, you can also drop `KILL cr` on `vshiftB_gfni`. It could be turned into an assert though (a runtime check halting the JVM on slow path in fastdebug build). ------------- PR Review Comment: https://git.openjdk.org/jdk/pull/33113#discussion_r4483713802
