OK, this is an important point for v2. The right way to do this is to add these variables to the mcp55 chip.h: add the lines u32 a0, a4, a8, ac, b0, b4;
Then, in the Config.lb for the mainboard, you do something like this in the section for the southbridge: register "a0" = "c1100001" register "a4" = "0" register "a8" = "0" register "ac" = "0" register "b0" = "02f40295" register "b4" = "085f0800" Then you add code to the mcp55 support to check these options and set them. If you have better names in mind go for it :-) It should look something like this, let me know if I missed something or this makes no sense. The existing use of register in mainboard/gigabyte/m57sli for the ide0_enable etc. can be used as a model. thanks ron -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
