See patch. The pnp_dev_info[] was incomplete and partly wrong, due to
me doing blind copy-paste. After checking with the datasheet I _think_
the contents are correct now, but it would be nice if someone could
double-check that.
Various other superios have the same problem I'm afraid, I'll post more
patches later...
For parallel port there are _two_ base addresses (0x60/0x61 and 0x62/0x63),
but most other superios/boards only use the first one (I assume the
second set is only needed for some non-standard parallel port modes?)
Also, I left IT8712F_GPIO "empty" like this
{&ops, IT8712F_GPIO, },
even though it does have 0x60/0x61, 0x62/0x63, and 0x64/0x65 base address
registers, but those are "SMI# Normal Run Access Base Address" and
"Simple I/O Base Address" and "Panel Button De-bounce Base Address",
which I guess we don't need (?)
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Fix/amend the incorrect pnp_dev_info[] items for the ITE IT8712F.
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Index: src/superio/ite/it8712f/superio.c
===================================================================
--- src/superio/ite/it8712f/superio.c (Revision 3625)
+++ src/superio/ite/it8712f/superio.c (Arbeitskopie)
@@ -121,15 +121,18 @@
.init = it8712f_init,
};
-/* TODO: FDC, MIDI, GAME, IR. */
static struct pnp_info pnp_dev_info[] = {
- {&ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0}, },
- {&ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x7f8, 0}, },
- {&ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
- {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},},
- {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4}, },
- {&ops, IT8712F_KBCM, PNP_IRQ0, },
- {&ops, IT8712F_GPIO, },
+ {&ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},},
+ {&ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
+ {&ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
+ {&ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},},
+ {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},},
+ {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},},
+ {&ops, IT8712F_KBCM, PNP_IRQ0,},
+ {&ops, IT8712F_GPIO, }, /* TODO? */
+ {&ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
+ {&ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},},
+ {&ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
};
static void enable_dev(struct device *dev)
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot