Uwe Hermann wrote:
See patch. The pnp_dev_info[] was incomplete and partly wrong, due to
me doing blind copy-paste. After checking with the datasheet I _think_
the contents are correct now, but it would be nice if someone could
double-check that.
Various other superios have the same problem I'm afraid, I'll post more
patches later...
For parallel port there are _two_ base addresses (0x60/0x61 and 0x62/0x63),
but most other superios/boards only use the first one (I assume the
second set is only needed for some non-standard parallel port modes?)
Yeah, that is interesting since there is only one IRQ. I have never seen
a second lpt port used. I would ignore it.
Also, I left IT8712F_GPIO "empty" like this
{&ops, IT8712F_GPIO, },
even though it does have 0x60/0x61, 0x62/0x63, and 0x64/0x65 base address
registers, but those are "SMI# Normal Run Access Base Address" and
"Simple I/O Base Address" and "Panel Button De-bounce Base Address",
which I guess we don't need (?)
You could put it in for completeness but I doubt it will ever get used.
Why did the io_info.mask change from 0x7f8 to 0xfff8/c/f? That just
changes the granularity of of the resource? It is not a mask on the
address. Also, what is io_info.set supposed to do? I didn't find any
reference to it in the code. Why is it sometimes set to 0x4? It would be
nice if io_info was documented a little.....
The IO/IRQ/DRQ flags for each device look correct.
Explain the io_info.mask then
Acked-by: Marc Jones <[EMAIL PROTECTED]>
Thanks,
Marc
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Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
http://www.amd.com/embeddedprocessors
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