Here are the major differences between v2 and v3 initializing serengeti cheetah. The biggest problem is that the memory-mapped I/O ends up in the wrong place (see the Display controller's ROM address)
I'll look at it more later, but if someone beats me to it I won't complain :) Thanks, Myles 0 6 0 AMD-8111 PCI v3 sets parity error response, v2 doesn't v2 has FD00FC00 for IO Base/LIM v3 has 01000000 1 4 0 Display Controller v3 sets parity error response, v2 doesn't v3 sets SERR# Enable, v2 doesn't v2 has FC000000 and FD053000 for base and lim v3 has 00000000 and 01055000 v2 has FD040001 v3 has 01040001 for ROM address 0 24 0 K8 [Athlon64/Opteron] HyperTransport Technology Configuration v2 thinks nodeID is 1 in 0x60 v3 doesn't enable the second processor in 0x68 v2 sets a reserved bit in 0x6c 0 24 1 K8 [Athlon64/Opteron] Address Map base and limits messed up in v3 using 0x012000 instead of 0x0fc000 in v2 base smaller than limit! 0xb8 & 0xbc in v3 limit 0xdc is 0x02020 v2 has 0x000. 0 24 2 K8 [Athlon64/Opteron] DRAM Controller reserved bits differ in 0x88 v2 sets reserved bit 12 in 0x94 0 24 3 K8 [Athlon64/Opteron] Miscellaneous Control 0x44 v2 sets bits 6, 25,27 27 is NB MCA to CPU 0 enable 0x80 & 0x84 power management totally different 0x90 & 0x94 v2 sets up the GART aperture, v3 doesn't 0xd4 & 0xd8 clock power & timing registers different.
v3.pci
Description: Binary data
v2.pci
Description: Binary data
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