On Thu, Oct 16, 2008 at 12:30 PM, Myles Watson <[EMAIL PROTECTED]> wrote:
> > Wait a second. The reason this is broken is that the code setting the PCI > decode register is in the ROM. Can we fix this by calling > pci_conf1_write_config32 instead? It looks like it's in RAM. > sure, but ANY call to ROM will fail. There is a huge hole: vga bios calls pcibios to set BAR 10 to ffffffff There is a huge window here: any call to ROM code will fail, so that includes printk (we do this on each pcibios call), and just about anything else. So we have a problem with a fundamental design decision ron -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
