I did not realize we had gone private. see below. Basically, vga bios tries to size a 16 meg register and at an intermediate point the vga hardware ends up decoding the top 16 mb of memory.
I welcome a fix. It's just not obvious to me. ron ---------- Forwarded message ---------- From: ron minnich <[EMAIL PROTECTED]> Date: Thu, Oct 16, 2008 at 12:15 PM Subject: Re: [coreboot] SimNOW VGA int 1a To: Marc Jones <[EMAIL PROTECTED]> Cc: Myles Watson <[EMAIL PROTECTED]>, Jordan Crouse <[EMAIL PROTECTED]> On Thu, Oct 16, 2008 at 12:08 PM, Marc Jones <[EMAIL PROTECTED]> wrote: > ron minnich wrote: >> >> well, hang on. >> >> I write ffffffff to BAR 10. >> Then what is left in BAR 10 is ff000000. That decodes to the top 16 MB >> of address space. At that point, all the memory goes bye bye. >> So do we really want the device enabled? >> >> Is this maybe a bug in the vga bios? This won't be an issue for code >> not running in the top 16 MB >> > > Yes it goes away but nothing should access it then. Put the BAR back and it > should be fine. but the EIP is accessing it then. We're running code at ffffxxxx. Here is the sequence: we're running at ffffxxxx. We write ffffffff at request of vgabios to the BAR 10. At that point vga is decoding ffxxxxxx. We can no longer fetch code from ffffxxxx. We go bye bye. Fix is to NOT compile the pcibios into stage0, or to also decode it into stage2. ron -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
