On Mon, Oct 27, 2008 at 3:43 PM, ron minnich <[EMAIL PROTECTED]> wrote:
> On Mon, Oct 27, 2008 at 2:37 PM, Myles Watson <[EMAIL PROTECTED]> wrote:
>
> > Have you applied my patch to add the 8132 so you can see it
> > working/breaking?
>
> can you give me a diff against current tree?
>
> thanks
>
> ron
Here it is:
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
I'm sorry it doesn't build but it's close and I have to go.
Thanks,
Myles
Index: southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- southbridge/amd/amd8132/amd8132_bridge.c (revision 954)
+++ southbridge/amd/amd8132/amd8132_bridge.c (working copy)
@@ -22,6 +22,7 @@
#include <lib.h>
#include <console.h>
#include <device/pci.h>
+#include <device/pcix.h>
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
@@ -422,12 +423,12 @@
struct device_operations amd8132_apic = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8132_IOAPIC}}},
+ .device = PCI_DEVICE_ID_AMD_8132_IOAPIC}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
- .phase4_enable_disable = ioapic_enable,
+ .phase4_enable_disable = ioapic_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase6_init = amd8132_ioapic_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &pci_ops_pci_dev,
};
Index: southbridge/amd/amd8111/amd8111.c
===================================================================
--- southbridge/amd/amd8111/amd8111.c (revision 954)
+++ southbridge/amd/amd8111/amd8111.c (working copy)
@@ -34,19 +34,19 @@
void amd8111_enable(struct device * dev)
{
- struct device * lpc_dev;
+ struct device * sub_dev;
struct device * bus_dev;
unsigned index;
unsigned reg_old, reg;
/* See if we are behind the amd8111 pci bridge */
bus_dev = dev->bus->dev;
- if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_AMD) &&
- (bus_dev->id.pci.device == PCI_DEVICE_ID_AMD_8111_PCI))
+ if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_AMD) &&
+ (bus_dev->id.pci.device == PCI_DEVICE_ID_AMD_8111_PCI))
{
unsigned devfn;
devfn = bus_dev->path.pci.devfn + (1 << 3);
- lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
+ sub_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
if (dev->path.pci.devfn == 2) { /* EHCI */
index = 16;
@@ -54,40 +54,40 @@
} else {
unsigned devfn;
devfn = (dev->path.pci.devfn) & ~7;
- lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
+ sub_dev = dev_find_slot(dev->bus->secondary, devfn);
index = dev->path.pci.devfn & 7;
}
- if ((!lpc_dev) || (index >= 17)) {
+ if ((!sub_dev) || (index >= 17)) {
return;
}
- if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_AMD) ||
- (lpc_dev->id.pci.device != PCI_DEVICE_ID_AMD_8111_ISA))
+ if ((sub_dev->id.pci.vendor != PCI_VENDOR_ID_AMD) ||
+ (sub_dev->id.pci.device != PCI_DEVICE_ID_AMD_8111_ISA))
{
u32 id;
- id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
+ id = pci_read_config32(sub_dev, PCI_VENDOR_ID);
if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) {
return;
}
}
if (index < 16) {
- reg = reg_old = pci_read_config16(lpc_dev, 0x48);
+ reg = reg_old = pci_read_config16(sub_dev, 0x48);
reg &= ~(1 << index);
if (dev->enabled) {
reg |= (1 << index);
}
if (reg != reg_old) {
- pci_write_config16(lpc_dev, 0x48, reg);
+ pci_write_config16(sub_dev, 0x48, reg);
}
}
else if (index == 16) {
- reg = reg_old = pci_read_config8(lpc_dev, 0x47);
+ reg = reg_old = pci_read_config8(sub_dev, 0x47);
reg &= ~(1 << 7);
if (!dev->enabled) {
reg |= (1 << 7);
}
if (reg != reg_old) {
- pci_write_config8(lpc_dev, 0x47, reg);
+ pci_write_config8(sub_dev, 0x47, reg);
}
}
}
Index: Kconfig
===================================================================
--- Kconfig (revision 954)
+++ Kconfig (working copy)
@@ -102,6 +102,8 @@
boolean
config SOUTHBRIDGE_NVIDIA_MCP55
boolean
+config SOUTHBRIDGE_AMD_AMD8132
+ boolean
config SOUTHBRIDGE_AMD_AMD8111
boolean
config SOUTHBRIDGE_AMD_SB600
Index: mainboard/amd/Kconfig
===================================================================
--- mainboard/amd/Kconfig (revision 954)
+++ mainboard/amd/Kconfig (working copy)
@@ -66,6 +66,7 @@
select CPU_AMD_K8
select NORTHBRIDGE_AMD_K8
select SOUTHBRIDGE_AMD_AMD8111
+ select SOUTHBRIDGE_AMD_AMD8132
select SUPERIO_WINBOND_W83627HF
select IOAPIC
help
Index: mainboard/amd/serengeti/defconfig
===================================================================
--- mainboard/amd/serengeti/defconfig (revision 954)
+++ mainboard/amd/serengeti/defconfig (working copy)
@@ -24,6 +24,7 @@
# CONFIG_VENDOR_PCENGINES is not set
CONFIG_MAINBOARD_DIR="amd/serengeti"
# CONFIG_BOARD_AMD_DB800 is not set
+# CONFIG_BOARD_AMD_DBM690T is not set
# CONFIG_BOARD_AMD_NORWICH is not set
CONFIG_BOARD_AMD_SERENGETI=y
# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
@@ -71,6 +72,7 @@
# Console
#
CONFIG_CONSOLE=y
+# CONFIG_CONSOLE_PREPEND_LOG_LEVEL is not set
CONFIG_CONSOLE_LOGLEVEL_8=y
# CONFIG_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_CONSOLE_LOGLEVEL_6 is not set
@@ -94,7 +96,7 @@
# Cosmetic console options
#
# CONFIG_CONSOLE_PREFIX is not set
-CONFIG_CONSOLE_BUFFER=y
+# CONFIG_CONSOLE_BUFFER is not set
#
# Devices
@@ -110,6 +112,7 @@
CONFIG_HW_MEM_HOLE_SIZEK=0x1000
CONFIG_NORTHBRIDGE_AMD_K8=y
CONFIG_SOUTHBRIDGE_AMD_AMD8111=y
+CONFIG_SOUTHBRIDGE_AMD_AMD8132=y
CONFIG_SUPERIO_WINBOND_W83627HF=y
#
Index: mainboard/amd/serengeti/dts
===================================================================
--- mainboard/amd/serengeti/dts (revision 954)
+++ mainboard/amd/serengeti/dts (working copy)
@@ -27,14 +27,11 @@
};
[EMAIL PROTECTED] {
/config/("northbridge/amd/k8/domain");
- [EMAIL PROTECTED],0{
- };
[EMAIL PROTECTED],0 {
/config/("northbridge/amd/k8/pci");
[EMAIL PROTECTED],0 {
/config/("southbridge/amd/amd8111/pci.dts");
[EMAIL PROTECTED],0{
- /config/("southbridge/amd/amd8111/nic.dts");
};
[EMAIL PROTECTED],0{
/config/("southbridge/amd/amd8111/usb.dts");
@@ -44,28 +41,34 @@
};
[EMAIL PROTECTED],2{
/config/("southbridge/amd/amd8111/usb2.dts");
+ disable;
};
- [EMAIL PROTECTED],0{
+ [EMAIL PROTECTED],0{
+ /config/("southbridge/amd/amd8111/nic.dts");
+ disable;
};
};
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/amd8111/lpc.dts");
};
- [EMAIL PROTECTED],1 {
+ [EMAIL PROTECTED],1 {
/config/("southbridge/amd/amd8111/ide.dts");
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/amd8111/smbus.dts");
};
- [EMAIL PROTECTED],3 {
+ [EMAIL PROTECTED],3 {
/config/("southbridge/amd/amd8111/acpi.dts");
};
- [EMAIL PROTECTED],5 {
+ [EMAIL PROTECTED],5 {
/config/("southbridge/amd/amd8111/ac97audio.dts");
};
- [EMAIL PROTECTED],6 {
+ [EMAIL PROTECTED],6 {
/config/("southbridge/amd/amd8111/ac97modem.dts");
};
+ [EMAIL PROTECTED],0 {
+ /config/("southbridge/amd/amd8132/pcix.dts");
+ };
};
[EMAIL PROTECTED],0 {
/config/("northbridge/amd/k8/pci");
Index: device/Makefile
===================================================================
--- device/Makefile (revision 954)
+++ device/Makefile (working copy)
@@ -33,5 +33,9 @@
STAGE2_DEVICE_SRC += hypertransport.c
endif
+# this is only needed for pcix devices
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
+STAGE2_DEVICE_SRC += pcix_device.c
+endif
$(obj)/device/pci_device.o: $(src)/device/pci_device.c $(obj)/statictree.h
--
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