On Fri, Oct 24, 2008 at 9:21 AM, Carl-Daniel Hailfinger < [EMAIL PROTECTED]> wrote:
> On 24.10.2008 17:13, Carl-Daniel Hailfinger wrote: > > Hi, > > > > I'm getting the following message from lspci on my K8 machine: > > > > 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 > > [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] > > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- > > ParErr- Stepping- SERR- FastB2B- DisINTx- > > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- > > <TAbort- <MAbort- >SERR- <PERR- INTx- > > Capabilities: [80] HyperTransport: Host or Secondary Interface > > !!! Possibly incomplete decoding for revision 1.02 > > Command: WarmRst+ DblEnd- > > Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- > > <CRCErr=0 > > Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit > > Revision ID: 1.02 > > Kernel modules: ipmi_si > > > > Note the warning about "Possibly incomplete decoding" which stems from > > the fact that the processor mentions HT revision 1.02 which is the last > > non-public revision. Every revision from 1.03 and beyond seems to be > > publically available. Now the big question is: Can we decode HT 1.02 > > like HT 1.03 or have there been fundamental changes in between? I'd like > > to create a patch for PCIutils (lspci) so we can have full info without > > a warning message. > >From the BKDG: 3.1 Configuration Space Accesses The AMD Athlon™ 64 and AMD Opteron™ Processors implement configuration space as defined in the PCI Local Bus Specification, Rev. 2.2, and the HyperTransport™ I/O Link Specification, Rev. 1.03. I read that to mean that even though the processor reports Rev 1.02, it's 1.03. Thanks, Myles
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
