> -----Original Message----- > From: ron minnich [mailto:[EMAIL PROTECTED] > Sent: Friday, November 07, 2008 9:24 AM > To: Myles Watson > Cc: Coreboot > Subject: Re: Subtractive Resources > > On Fri, Nov 7, 2008 at 7:18 AM, Myles Watson <[EMAIL PROTECTED]> wrote: > > I'm running into a problem when resources are read. > > > > The amd8111 adds two subtractive resources on link 0. The problem is > that > > it has no link 0. > > This is usually a sign that I got the dtc wrong somehow. > > Here is v2: > struct device _dev15 = { > .ops = 0, > .bus = &_dev8.link[0], > .path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = > PCI_DEVFN(0x0,0)}}}, > .enabled = 1, > .on_mainboard = 1, > .link = { > [0] = { > .link = 0, > .dev = &_dev15, > .children = &_dev16, > }, > }, > .links = 1, > .sibling = &_dev20, > .chip_ops = &southbridge_amd_amd8111_ops, > .chip_info = &southbridge_amd_amd8111_info_14, > .next=&_dev16 > }; > > and > > struct device _dev16 = { > .ops = 0, > .bus = &_dev15.link[0], > .path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = > PCI_DEVFN(0x0,0)}}}, > .enabled = 1, > .on_mainboard = 1, > .link = { > }, > .links = 0, > .sibling = &_dev17, > .chip_ops = &southbridge_amd_amd8111_ops, > .chip_info = &southbridge_amd_amd8111_info_14, > .next=&_dev17 > }; > > > So the amd8111 is a bridge that needs resources.
My understanding is that the amd8111 _has_ a bridge, but the device that is causing the problem is lpc, which is not a bridge, nor behind the amd8111's bridge. So when its resources are read and it is found to have subtractive resources, the code tries to descend. It doesn't have a bus, and this fails. > That said, you said your change fixes it. Does that mean serengeti > works? It's hard to see how given that this is a bridge. Sorry I wasn't more clear. I meant that the fix no longer tries to call functions with NULL pointers. I don't think the dts is wrong, but I think that there are a lot fewer intermediaries in v3 then there were in v2. Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
