> -----Original Message----- > From: Rudolf Marek [mailto:[EMAIL PROTECTED] > Sent: Tuesday, December 02, 2008 7:56 AM > To: Myles Watson > Cc: 'Marc Jones'; 'Coreboot' > Subject: Re: [coreboot] Resource Allocation discussion > > > ------- From k8t890_traf_ctrl.c ------ > > > > pci_dev_read_resources(dev); > > > > res = new_resource(dev, 0x40); > > /* NB APIC fixed to this address. */ > > res->base = K8T890_APIC_BASE; > > res->size = 256; > > res->limit = res->base + res->size - 1; > > res->align = 8; > > res->gran = 8; > > res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | > > IORESOURCE_STORED | IORESOURCE_ASSIGNED; > > > > /* Add an MMCONFIG resource. */ > > res = new_resource(dev, K8T890_MMCONFIG_MBAR); > > res->size = 256 * 1024 * 1024; > > res->align = log2(res->size); > > res->gran = log2(res->size); > > res->limit = 0xffffffff; /* 4G */ > > res->flags = IORESOURCE_MEM; > > > > ------- end ---------- > > Yes now I remember that I wrote the code ;) so please disregard mine > previous > mail about _LOW and _STATIC_HIGH.
:) I'm wondering why the size of the APIC region here is 256. That's smaller than any reference from the resource map link you sent. > Problem is that some resources needs to go to ACPI. And it is needed to > > 1) store them in some ACPI table during table construction, read resource > should > work. > > 2) worse case - store in AML code. This can be done by some SSDT hacks > which is > ugly or write AML code which re-reads the resources from hardware. Which device should logically own the ACPI resources? We can just allocate them there. I vote for the domain or the mainboard (root device) to own them. > > Ad 1) > http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot- > v2/src/mainboard/asus/a8v-e_se/fadt.c > http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot- > v2/src/mainboard/asus/a8v-e_se/acpi_tables.c > > Ad 2) > > http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot- > v2/src/northbridge/amd/amdk8/ssdt.dsl > http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot- > v2/src/mainboard/agami/aruma/acpi_tables.c > > In fact #2 as in ARUMA and proper DSDT code which handles _CSR (CRS?) > resources > is neccessary for Windows to boot properly. Check the Aruma DSDT: > > http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot- > v2/src/mainboard/agami/aruma/dx/dsdt_lb.dsl > > (In particular Method (_CRS, 0, NotSerialized) for PCI0). I'm in too deep here. I'm hoping that we can figure out resource allocation a little better before we move on to ACPI tables. Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
