On Thu, Jun 25, 2009 at 2:46 AM, Bao, Zheng<[email protected]> wrote: > amd_fam10_ht_sb_only.diff: > I am not sure about this patch. Not sure to add signed-off-by line. > Don't ack it before review it and say something. > > My board is Fam10 + 1 HT SouthBridge. It is close to dbm690t. So I > set HT_CHAIN_UNITID_BASE as 0 and HT_CHAIN_END_UNITID_BASE as 1, even > though I don't know well what they actually are. Base on currently fam10 > code, I have skip some code, otherwise the HT link can not be set up > correctly. It is pretty like a workaround and my board can work in > 1.8GHz (HT3). Doesn't the code in repository cover the mode of > one HT processor + 1 HT SB device? >
I assume that you are getting a failure since you skipped a section and commented out a halt on error. What do you get for AMD_CB_EventNotify? You can get more information about bus numbering in the HTIOlink spec and the device spec should have any requirements for bus numbering. http://www.hypertransport.org/docs/tech/HTC20051222-0046-0008-Final-4-21-06.pdf But, I assume that the device will work like the 690, so the setting should be ok but compare with the vendor bios. > ****************************************************************** > amd_fam10_mct_am2_rough.diff: > The original code was pretty weird. It definitely can not > be build correctly. This patch is only about building error. > > The mctardk4 seems to be for AM2. Based on the code and this > patch, the memory seems to work but is unstable and unbearably > slow. I need to dig it more. > > Since I am confused about this, it is not a signed-off-by patch. AM2 was never built, just ported for reference. There wasn't a product at the time. I dontt know if the Bx table will work for Cx. You will need to work with Tim and the BIOS group to get the settings. You might need to add a fam10 version of the socket similar to the socket f in /src/cpu/amd. Marc -- http://marcjonesconsulting.com -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
