-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello,
Following patch reworks car_disable into C. Tested, works here. I compared also the GCC generated code and it looks all right. Please test on some multicore CPU. I added the "memory" clobber to read_cr0 / write_cr0 function as it is in Linux Kernel. Seems that if this is missing, GCC is too smart and messes the order of reads/writes to CR0 (not tested if really a problem here, but be safe for future users of this function ;) Signed-off-by: Rudolf Marek <[email protected]> Maybe we can add nice copyright header too? Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvwIWoACgkQ3J9wPJqZRNV7/QCcD+WycESr5QIRGThVOX0UJmjL I0wAn39m4vC0SdvZdFLoI23cxPMyEQb1 =qavi -----END PGP SIGNATURE-----
Index: src/include/cpu/x86/cache.h
===================================================================
--- src/include/cpu/x86/cache.h (revision 5511)
+++ src/include/cpu/x86/cache.h (working copy)
@@ -20,16 +20,19 @@
#ifndef CPU_X86_CACHE
#define CPU_X86_CACHE
+/* the memory clobber prevents the GCC from reordering the read/write order
+ of CR0 */
+
static inline unsigned long read_cr0(void)
{
unsigned long cr0;
- asm volatile ("movl %%cr0, %0" : "=r" (cr0));
+ asm volatile ("movl %%cr0, %0" : "=r" (cr0) :: "memory");
return cr0;
}
static inline void write_cr0(unsigned long cr0)
{
- asm volatile ("movl %0, %%cr0" : : "r" (cr0));
+ asm volatile ("movl %0, %%cr0" : : "r" (cr0) : "memory");
}
static inline void invd(void)
@@ -39,7 +42,7 @@
static inline void wbinvd(void)
{
- asm volatile ("wbinvd");
+ asm volatile ("wbinvd" ::: "memory");
}
static inline void enable_cache(void)
Index: src/cpu/amd/car/disable_cache_as_ram.c
===================================================================
--- src/cpu/amd/car/disable_cache_as_ram.c (revision 5511)
+++ src/cpu/amd/car/disable_cache_as_ram.c (working copy)
@@ -1,46 +1,37 @@
-/* by yhlu 6.2005 */
-/* be warned, this file will be used other cores and core 0 / node 0 */
+/* original idea yhlu 6.2005
+
+(C) Rudolf Marek <[email protected]>
+
+be warned, this file will be used other cores and core 0 / node 0
+
+*/
+
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
- __asm__ __volatile__ (
- /* We don't need cache as ram for now on */
+ msr_t msr;
+
/* disable cache */
- "movl %%cr0, %%eax\n\t"
- "orl $(0x1<<30),%%eax\n\t"
- "movl %%eax, %%cr0\n\t"
+ write_cr0(read_cr0() | (1 << 30));
- /* clear sth */
- "movl $0x269, %%ecx\n\t" /* fix4k_c8000*/
- "xorl %%edx, %%edx\n\t"
- "xorl %%eax, %%eax\n\t"
- "wrmsr\n\t"
+ msr.lo = 0;
+ msr.hi = 0;
+ wrmsr(MTRRfix4K_C8000_MSR, msr);
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
- "movl $0x268, %%ecx\n\t" /* fix4k_c0000*/
- "wrmsr\n\t"
+ wrmsr(MTRRfix4K_C0000_MSR, msr);
#endif
-
/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
- "movl $0xC0010010, %%ecx\n\t"
-// "movl $SYSCFG_MSR, %ecx\n\t"
- "rdmsr\n\t"
- "andl $(~(3<<18)), %%eax\n\t"
-// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
- "wrmsr\n\t"
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
+ wrmsr(SYSCFG_MSR, msr);
+
/* Set the default memory type and disable fixed and enable variable MTRRs */
- "movl $0x2ff, %%ecx\n\t"
-// "movl $MTRRdefType_MSR, %ecx\n\t"
- "xorl %%edx, %%edx\n\t"
- /* Enable Variable and Disable Fixed MTRRs */
- "movl $0x00000800, %%eax\n\t"
- "wrmsr\n\t"
+ msr.hi = 0;
+ msr.lo = (1 << 11);
- /* enable cache */
- "movl %%cr0, %%eax\n\t"
- "andl $0x9fffffff,%%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- ::: "memory", "eax", "ecx", "edx"
- );
+ wrmsr(MTRRdefType_MSR, msr);
+
+ enable_cache();
}
static void disable_cache_as_ram_bsp(void)
make_disable_a_c.patch.sig
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