-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi,
My plan is to add backup code for S3 into post_cache_as_ram, I have it working already but needs cleanup. POC is in [PATCH] WIP - suspend/resume on AMD64 using CBMEM. Also I think we could enable whole ROM for caching in the enable_cache_as_ram. It works fine here. As the last point, just right after post_cache_as_ram I would like to setup following MTRR instead of _RAMBASE - _RAMTOP 0MB - TOM WB (or little over TOM if tom not a power of 2?) 0xA0000 - 0xC0000 UC I think one could live with this setup until the MTRR are set again in ramstage. More ideas? Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvwZFYACgkQ3J9wPJqZRNUeeQCgvmc6+zv7kj11rdFiGAvZY40M /2gAn3b/oMebk076ukXknWoiOJ8PcSmf =asle -----END PGP SIGNATURE----- -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
