Am 07.09.2010 01:23, schrieb Kevin O'Connor:
> Enable TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 by default. Without this
> set, almost all boards use the inb(0x80) method. Unfortunately, that
> method takes over a second to calibrate, and it's results are not as
> reliable.
>
> There is a chance that some boards may not work well with the timer2
> method. This is likely rare, because both libpayload and seabios use
> the timer2 method unconditionally and there has not been reports of an
> issue. Should a board not support the more accurate timer2 mechanism,
> it will need to be updated to actively disable it.
How about this instead? It allows boards that require the workaround to
simply "select" it.
Signed-off-by: Patrick Georgi <[email protected]>
Index: src/cpu/x86/Kconfig
===================================================================
--- src/cpu/x86/Kconfig (Revision 5777)
+++ src/cpu/x86/Kconfig (Arbeitskopie)
@@ -19,7 +19,7 @@
bool
default n
-config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+config TSC_CALIBRATE_WITH_IO
bool
default n
Index: src/cpu/x86/tsc/delay_tsc.c
===================================================================
--- src/cpu/x86/tsc/delay_tsc.c (Revision 5777)
+++ src/cpu/x86/tsc/delay_tsc.c (Arbeitskopie)
@@ -7,7 +7,7 @@
static unsigned long clocks_per_usec;
-#if (CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 == 1)
+#if !CONFIG_TSC_CALIBRATE_WITH_IO
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
/* ------ Calibrate the TSC -------
@@ -82,7 +82,7 @@
return 0;
}
-#else /* CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 */
+#else /* CONFIG_TSC_CALIBRATE_WITH_IO */
/*
* this is the "no timer2" version.
Index: src/southbridge/amd/cs5536/Kconfig
===================================================================
--- src/southbridge/amd/cs5536/Kconfig (Revision 5777)
+++ src/southbridge/amd/cs5536/Kconfig (Arbeitskopie)
@@ -19,12 +19,5 @@
config SOUTHBRIDGE_AMD_CS5536
bool
- select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+ select UDELAY_TSC
-config UDELAY_TSC
- bool
- default y
- depends on SOUTHBRIDGE_AMD_CS5536
-
-
-
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
