While we are at it. I'm attaching some very old patch (r2978 ;)
which contains some errata fixes too, if you have some spare time please try to
check if it is correct.
Signed-off-by: Rudolf Marek <[email protected]>
Thanks,
Rudolf
Index: src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- src/cpu/amd/model_fxx/model_fxx_init.c (revision 2978)
+++ src/cpu/amd/model_fxx/model_fxx_init.c (working copy)
@@ -368,6 +368,7 @@
static inline void k8_errata(void)
{
msr_t msr;
+ u32 cpuid;
#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Erratum 63... */
@@ -439,7 +440,7 @@
#endif
#if K8_REV_F_SUPPORT == 0
- if (!is_cpu_pre_e0())
+ if (!is_cpu_pre_d0())
#endif
{
/* Erratum 110 ... */
@@ -453,13 +454,19 @@
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
-#if K8_REV_F_SUPPORT == 1
- /* Erratum 131... */
+ /* Erratum 131 is fixed together with erratum 169 */
msr = rdmsr(NB_CFG_MSR);
- msr.lo |= 1 << 20;
+ msr.lo |= 1 << 32;
wrmsr(NB_CFG_MSR, msr);
-#endif
+ cpuid = cpuid_eax(0x1);
+
+ /* Fixme erratum 113 JH-E1 DH-E3 */
+ if ((cpuid == 0x20f10) || (cpuid == 0x20FF0) || (cpuid == 0x20FC0)) {
+ msr = rdmsr_amd(BU_CFG_MSR);
+ msr.hi |= (1 << (48 - 32));
+ wrmsr_amd(BU_CFG_MSR, msr);
+ }
}
extern void model_fxx_update_microcode(unsigned cpu_deviceid);
===================================================================
--- src/northbridge/amd/amdk8/coherent_ht.c (revision 2978)
+++ src/northbridge/amd/amdk8/coherent_ht.c (working copy)
@@ -1704,6 +1704,12 @@
needs_reset = 1; /* Needed? */
}
}
+ /* Errata 169 */
+ dev = NODE_HT(node);
+ cmd = pci_read_config32(dev, 0x68);
+ cmd &= ~(3 << 21);
+ cmd |= (1 << 21);
+ pci_write_config32(dev, 0x68, cmd);
#endif
}
return needs_reset;
Index: src/northbridge/amd/amdk8/amdk8.h
===================================================================
--- src/northbridge/amd/amdk8/amdk8.h (revision 2978)
+++ src/northbridge/amd/amdk8/amdk8.h (working copy)
@@ -135,6 +135,8 @@
#define DCL_QFC_EN (1<<2)
#define DCL_DisDqsHys (1<<3)
#define DCL_Burst2Opt (1<<5)
+/* Check errata 115 for JH-E1 */
+/* Check errata 116 */
#define DCL_DramInit (1<<8)
#define DCL_DualDIMMen (1<<9)
#define DCL_DramEnable (1<<10)
Index: src/northbridge/amd/amdk8/coherent_ht_car.c
===================================================================
--- src/northbridge/amd/amdk8/coherent_ht_car.c (revision 2978)
+++ src/northbridge/amd/amdk8/coherent_ht_car.c (working copy)
@@ -1703,6 +1703,12 @@
needs_reset = 1; /* Needed? */
}
}
+ /* Errata 169 */
+ dev = NODE_HT(node);
+ cmd = pci_read_config32(dev, 0x68);
+ cmd &= ~(3 << 21);
+ cmd |= (1 << 21);
+ pci_write_config32(dev, 0x68, cmd);
#endif
}
return needs_reset;
--
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