> Hi, > sorry for the misunderstanding. > Setting bit 32 in msr should be -> 'msr.hi |= (1<< 0)', no? LOL! Nice catch.
This is what happens when you're still up at 6AM, obsessive drawing lines on a Google Earth printscreen in order to finish a project due in a few hours. :P It's funny to see those logic mistakes made with so much ease. As for #169, we should set 'msr.hi |= (1<< 0)' :P, "set F0x68[22:21](DsNpReqLmt0) to 01b," and drop #131 altogether. I'm assuming the second part means 0:18.0, register 0x6b-0x68[22:21], or Rx6a[6-5]. reg = pci_read_config8(0:18.0, 0x6a); reg |= 0x20; pci_write_config8(0:18.0, 0x6a, reg); Alex -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
