see patch
Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode). No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart VSRamp in step b
of 2.4.1.7 BKDG to its own function.
Signed-off-by: Xavi Drudis Ferran <[email protected]>
--- src/cpu/amd/model_10xxx/fidvid.c 2011-02-16 20:51:55.000000000 +0100
+++ src/cpu/amd/model_10xxx/fidvid.c 2011-02-16 20:51:55.000000000 +0100
@@ -66,6 +66,21 @@ static void enable_fid_change(u8 fid)
}
}
+static void setVSRamp(device_t dev) {
+ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime]
+ * If this field accepts 8 values between 10 and 500 us why
+ * does page 324 say "BIOS should set this field to 001b."
+ * (20 us) ?
+ * Shouldn't it depend on the voltage regulators, mainboard
+ * or something ?
+ */
+ u32 dword;
+ dword = pci_read_config32(dev, 0xd8);
+ dword &= VSRAMP_MASK;
+ dword |= VSRAMP_VALUE;
+ pci_write_config32(dev, 0xd8, dword);
+}
+
static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
{
u8 pviModeFlag;
@@ -179,11 +194,8 @@ static void prep_fid_change(void)
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
dev = NODE_PCI(i, 3);
- dword = pci_read_config32(dev, 0xd8);
- dword &= VSRAMP_MASK;
- dword |= VSRAMP_VALUE;
- pci_write_config32(dev, 0xd8, dword);
-
+ setVSRamp(dev);
+ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
/* Figure out the value for VsSlamTime and program it */
recalculateVsSlamTimeSettingOnCorePre(dev);
--
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