see patch
Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj], Northbridge/core synchronization FIFO pointer adjust, to its own function. Signed-off-by: Xavi Drudis Ferran <[email protected]> --- src/cpu/amd/model_10xxx/fidvid.c 2011-02-16 20:51:55.000000000 +0100 +++ src/cpu/amd/model_10xxx/fidvid.c 2011-02-16 20:51:55.000000000 +0100 @@ -258,6 +258,17 @@ static void config_power_ctrl_misc_reg(d } } + +static void config_nb_syn_ptr_adj(device_t dev) { + /* Note the following settings are additional from the ported + * function setFidVidRegs() + */ + u32 dword = pci_read_config32(dev, 0xDc); + dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ + pci_write_config32(dev, 0xdc, dword); + +} + static void prep_fid_change(void) { u32 dword; @@ -281,13 +292,8 @@ static void prep_fid_change(void) config_clk_power_ctrl_reg0(i); config_power_ctrl_misc_reg(dev); - - /* Note the following settings are additional from the ported - * function setFidVidRegs() - */ - dword = pci_read_config32(dev, 0xDc); - dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ - pci_write_config32(dev, 0xdc, dword); + + config_nb_syn_ptr_adj(dev); /* Rev B settings - FIXME: support other revs. */ dword = 0xA0E641E6;
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
