Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1827
-gerrit commit 68483dbc3075f136b9cccc3481926fef3af02839 Author: Marc Jones <[email protected]> Date: Fri Nov 2 14:26:44 2012 -0600 Sandybridge: Set PEG clock gating If the PEI System Agent doesn't run PCIe initialization, the PEG clock gating will not be setup. Add the PEG clock gating when pei_data->pcie_init is 0. Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce Signed-off-by: Marc Jones <[email protected]> --- src/northbridge/intel/sandybridge/raminit.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2b46873..b5a1c23 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -205,6 +205,13 @@ static void report_memory_config(void) } } +static void post_system_agent_init(struct pei_data *pei_data) +{ + /* If PCIe init is skipped, set the PEG clock gating */ + if (!pei_data->pcie_init) + MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; +} + /** * Find PEI executable in coreboot filesystem and execute it. * @@ -289,6 +296,7 @@ void sdram_initialize(struct pei_data *pei_data) else intel_early_me_status(); + post_system_agent_init(pei_data); report_memory_config(); /* S3 resume: don't save scrambler seed or MRC data */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
