I thought microcode files are kind of patches for CPU, it suppose to be loaded before MRC just in case it fixes any issues related with CPU. I actually did encounter an system random halt issue related with no loading microcode before MRC training.
Martin, how do you think to display a warning during coreboot compiling if PLATFORM_USES_FSP selected but microcode does not configure properly. On Wed, Jun 4, 2014 at 5:43 PM, Martin Roth <[email protected]> wrote: > Thanks Paul. > > I'm working on a fix for this. Right now the option get selected correctly > if you set it at the first menuconfig run. If you go back and select the > microcode options later, they don't get correctly enabled even though > they're turned on with a select statement. > > I hope to have a patch up for this today. > > Martin > > > > > On 06/03/2014 04:17 PM, Paul Menzel wrote: > >> Dear Gerald, >> >> >> Am Dienstag, den 03.06.2014, 14:03 +0200 schrieb Gerald Otter: >> >> I am trying to run coreboot + seabios payload on the bayley bay crb >>> with the recently committed FSP integration, but have had no luck so >>> far. >>> This crb uses the bay trail I (now atom e3800) soc from intel. >>> >>> Following the instructions from commit d75800c7f , I have built a 2MB >>> image and flashed it to the upper 2MB of the 8MB flash, leaving the >>> TXE / flash descriptor intact. >>> I have added the config from the build. The FSP I used is >>> BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014, together with the flash >>> descriptor and TXE from the 80.21 bios provided by intel, and vga bios >>> 36.2.2. >>> Fwiw, I have tried both the 32bit and 64bit releases of the bios, even >>> though the flash descriptor and TXE binary seem to be exactly the >>> same. >>> >>> The issue I’m running into is that I have no idea if anything is >>> running at all. >>> There is no output on the VGA/HDMI ports or uart. >>> >>> The legacy uart referred to in the source is working correctly with >>> the original intel bios, but does not produce any output with the >>> coreboot image. >>> I have tried the most common baud rates (115200, 19200, 9600 ) and did >>> some measurements with a scope in case I got the baud rate wrong, but >>> no cigar. >>> The uart I’m using is the PCU uart, as opposed to hsuart1/2 and the >>> superIO uart. This matches with the configuration in coreboot when >>> compared to the datasheet, so I’m assuming I got this set up >>> correctly. >>> Unfortunately, this is about all the information I have, so I hope I >>> am missing something obvious when building the image / flashing it, >>> etc. >>> >> […] >> >> it looks like you are missing the microcode. (Next time please also send >> the output of `build/cbfstool build/coreboot.rom print`.) >> >> Could you please test if selecting “Generate from tree” in the prompt >> “Include CPU microcode in CBFS”? >> >> In the `.config`, instead of >> >> # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set >> # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set >> CONFIG_CPU_MICROCODE_CBFS_NONE=y >> >> you should have the one below. >> >> CONFIG_CPU_MICROCODE_CBFS_GENERATE=y >> # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set >> # CONFIG_CPU_MICROCODE_CBFS_NONE is not set >> >> >> Thanks, >> >> Paul >> >> >> > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot >
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